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(parent: 4af58f1) | patch
Improve ARM64 vector creation
authorLouis Gerbarg <lgg@apple.com>
Thu, 17 Apr 2014 20:51:50 +0000 (20:51 +0000)
committerLouis Gerbarg <lgg@apple.com>
Thu, 17 Apr 2014 20:51:50 +0000 (20:51 +0000)
commit5540570374a374e702bce1c2fa4208ebe9433d74
treeb38874f2f08f19eefc9fe435bb4552a750ab3a9atree | snapshot
parent4af58f145d7dececbd866c7f8e942cbfc5801d90commit | diff
Improve ARM64 vector creation

This patch improves the performance of vector creation in caseiswhere where
several of the lanes in the vector are a constant floating point value. It
also includes new patterns to fold together some of the instructions when the
value is 0.0f. Test cases included.

rdar://16349427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM64/ARM64ISelLowering.cpp diff | blob | history
lib/Target/ARM64/ARM64InstrInfo.td diff | blob | history
test/CodeGen/ARM64/vector-insertion.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors