Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks
authorWeiming Zhao <weimingz@codeaurora.org>
Mon, 13 Jan 2014 18:47:54 +0000 (18:47 +0000)
committerWeiming Zhao <weimingz@codeaurora.org>
Mon, 13 Jan 2014 18:47:54 +0000 (18:47 +0000)
commit436f2975ace26abec6a686ef74fec728d5d52aa4
treee60982a9cdcfbbf5e8b370ef60de2134997f9fca
parent99c7fec2c94bd44fd16ba50340896287438e6a0e
Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks

The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/Thumb2SizeReduction.cpp
test/CodeGen/Thumb2/2011-12-16-T2SizeReduceAssert.ll