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(parent: 7462aea) | patch
Add the following 64-bit vector integer arithmetic instructions added in POWER8:
authorKit Barton <kbarton@ca.ibm.com>
Tue, 3 Mar 2015 19:55:45 +0000 (19:55 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Tue, 3 Mar 2015 19:55:45 +0000 (19:55 +0000)
commit40057e8ee838cf8a529ed4bed98abc8bde1bda2a
treeb4633d5171f959c7845988ee50a5c428254910dctree | snapshot
parent7462aeac16aba76d06276c18fa1342407fb14833commit | diff
Add the following 64-bit vector integer arithmetic instructions added in POWER8:

vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231115 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
include/llvm/IR/IntrinsicsPowerPC.td diff | blob | history
lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff | blob | history
lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
lib/Target/PowerPC/PPCInstrAltivec.td diff | blob | history
lib/Target/PowerPC/PPCSchedule.td diff | blob | history
lib/Target/PowerPC/README_ALTIVEC.txt diff | blob | history
test/CodeGen/PowerPC/vec_add_sub_doubleword.ll [new file with mode: 0644] blob
test/CodeGen/PowerPC/vec_cmpd.ll [new file with mode: 0644] blob
test/CodeGen/PowerPC/vec_minmax.ll [new file with mode: 0644] blob
test/CodeGen/PowerPC/vec_mul_even_odd.ll [new file with mode: 0644] blob
test/CodeGen/PowerPC/vec_rotate_shift.ll [new file with mode: 0644] blob
test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt diff | blob | history
test/MC/PowerPC/ppc64-encoding-vmx.s diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors