Fix a bug in DAGcombiner about zero-extend after setcc.
authorKevin Qin <Kevin.Qin@arm.com>
Mon, 30 Dec 2013 02:05:13 +0000 (02:05 +0000)
committerKevin Qin <Kevin.Qin@arm.com>
Mon, 30 Dec 2013 02:05:13 +0000 (02:05 +0000)
commit3f8f3c9feb2e10e1f936dee23973b56bc361722d
treee5edea256fec094a9d832f297210f3394ce5364c
parent3796015b5bcaa1a27ff1a6816a8c87bd58d8629b
Fix a bug in DAGcombiner about zero-extend after setcc.

For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/AArch64/neon-shift-left-long.ll