ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chips
authorChristian Daudt <csd@broadcom.com>
Thu, 9 May 2013 21:21:01 +0000 (22:21 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 15 May 2013 18:39:27 +0000 (19:39 +0100)
commit3b656fed6ff65d6d268da9ed0760c2a58d125771
tree17ec053049fedb78e072fbafd055e8ba712422b2
parentfaefd550c45d8d314e8f260f21565320355c947f
ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chips

Rev A2 SoCs have an unorthodox memory re-mapping and this needs
to be reflected in the cache operations.
This patch adds new outer cache functions for the l2x0 driver
to support this SoC revision. It also adds a new compatible
value for the cache to enable this functionality.

Updates from V1:
- remove section 1 altogether and note that in comments
- simplify section selection caused by section 1 removal
- BUG_ON just in case section 1 shows up

Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Documentation/devicetree/bindings/arm/l2cc.txt
arch/arm/boot/dts/bcm11351.dtsi
arch/arm/mm/cache-l2x0.c