Add support for targets (like Alpha) that have terminator instructions which

Add support for targets (like Alpha) that have terminator instructions which
use virtual registers.  We now allow the first instruction in a block of
terminators to use virtual registers, and update phi elimination to correctly
update livevar when eliminating phi's.  This fixes a problem on a testcase
Andrew sent me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25083 91177308-0d34-0410-b5e6-96231b3b80d8