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(parent: a2f8d37) | patch
ARM FastISel fix load register classes
authorJF Bastien <jfb@google.com>
Sun, 9 Jun 2013 00:20:24 +0000 (00:20 +0000)
committerJF Bastien <jfb@google.com>
Sun, 9 Jun 2013 00:20:24 +0000 (00:20 +0000)
commit1fe907e7f2de32df894373e24a10c8f54534d770
tree3f4d677ccc95df7078549813d931bfed6a3a66d7tree | snapshot
parenta2f8d37fb791d197e7b0b8e6edfa6535f6b21602commit | diff
ARM FastISel fix load register classes

The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.

These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183624 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMFastISel.cpp diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors