[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
authorDaniel Sanders <daniel.sanders@imgtec.com>
Thu, 12 Jun 2014 15:00:17 +0000 (15:00 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Thu, 12 Jun 2014 15:00:17 +0000 (15:00 +0000)
commit1f4c755c2cb31f5b812734428a28bb11fd27639a
treeec2e1eab6b78846387d0e01180f19f85752514d1
parent159b95c4842e4b0ad4734c1d92d341bd40100c86
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
24 files changed:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
lib/Target/Mips/MicroMipsInstrFPU.td
lib/Target/Mips/Mips32r6InstrInfo.td
lib/Target/Mips/MipsInstrFPU.td
lib/Target/Mips/MipsSEISelLowering.cpp
test/CodeGen/Mips/analyzebranch.ll
test/CodeGen/Mips/fpbr.ll
test/MC/Mips/mips1/invalid-mips4.s
test/MC/Mips/mips1/invalid-mips5.s
test/MC/Mips/mips1/valid.s
test/MC/Mips/mips2/invalid-mips32.s
test/MC/Mips/mips2/invalid-mips32r2.s
test/MC/Mips/mips2/invalid-mips4.s
test/MC/Mips/mips2/invalid-mips5.s
test/MC/Mips/mips2/valid.s
test/MC/Mips/mips3/invalid-mips4.s
test/MC/Mips/mips3/invalid-mips5.s
test/MC/Mips/mips3/valid.s
test/MC/Mips/mips32/valid.s
test/MC/Mips/mips32r2/valid.s
test/MC/Mips/mips4/valid.s
test/MC/Mips/mips5/valid.s
test/MC/Mips/mips64/valid.s
test/MC/Mips/mips64r2/valid.s