Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some...
authorSilviu Baranga <silviu.baranga@arm.com>
Thu, 5 Apr 2012 16:19:29 +0000 (16:19 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Thu, 5 Apr 2012 16:19:29 +0000 (16:19 +0000)
commit1c01249191ba5d3648e7bedaf8233c41cc103551
treed1ccb1b1271b6d4b01c63eef2549bb96110b222e
parent82e1bba0e4afaf3769fc46819c1601e387ffb56e
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrInfo.td
test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt [new file with mode: 0644]