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MIPS: Octeon: Make interrupt controller work with threaded handlers.
authorDavid Daney <david.daney@cavium.com>
Thu, 5 Apr 2012 17:24:25 +0000 (10:24 -0700)
committerDavid Daney <david.daney@cavium.com>
Fri, 31 Aug 2012 17:46:54 +0000 (10:46 -0700)
commit1a7e68f2c7f1e3bd6c49df031ec0eca947c35b2d
tree2576f5805f29307b199d11928d8f48bb3f4752batree | snapshot
parent88fd85892a55730878fc081eee62553eb18f1b9ccommit | diff
MIPS: Octeon: Make interrupt controller work with threaded handlers.

For CIUv1 controllers, we were relying on all calls to the irq_chip
functions to be done from the CPU that received the irq, and that they
would all be done from interrupt contest.  These assumptions do not
hold for threaded handlers.

We make all the masking actually mask the irq source, and use real
raw_spin_locks instead of manually twiddling the Status[IE] bit.

Signed-off-by: David Daney <david.daney@cavium.com>
arch/mips/cavium-octeon/octeon-irq.c diff | blob | history
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