- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the

- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
  memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8