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[AArch64] Scale offsets by the size of the memory operation. NFC.
authorChad Rosier <mcrosier@codeaurora.org>
Tue, 29 Sep 2015 16:07:32 +0000 (16:07 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Tue, 29 Sep 2015 16:07:32 +0000 (16:07 +0000)
commit0ee7f2ef5cadacbeec590c7bffc0a4363074ea5d
treef34b9b554ee2b4f179fff711f8547e8dccee012btree | snapshot
parenta9db22a72adfa23572762457a88d104085f97f6dcommit | diff
[AArch64] Scale offsets by the size of the memory operation. NFC.

The immediate in the load/store should be scaled by the size of the memory
operation, not the size of the register being loaded/stored.  This change gets
us one step closer to forming LDPSW instructions.  This change also enables
pre- and post-indexing for halfword and byte loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248804 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors