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(parent: f90c8c7) | patch
FastISel: constrain the RegClass of operands when emitting instructions.
authorTim Northover <tnorthover@apple.com>
Tue, 15 Apr 2014 13:59:49 +0000 (13:59 +0000)
committerTim Northover <tnorthover@apple.com>
Tue, 15 Apr 2014 13:59:49 +0000 (13:59 +0000)
commit03eecdccff8d3f69412d9cbcb07c0ace7709e1e4
tree38c54f1ebc6af103c2098d293e947b582ba53237tree | snapshot
parentf90c8c7063f349781a50bfb984f28af33e2b6778commit | diff
FastISel: constrain the RegClass of operands when emitting instructions.

ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.

More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206283 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/FastISel.h diff | blob | history
lib/CodeGen/SelectionDAG/FastISel.cpp diff | blob | history
lib/Target/ARM/ARMFastISel.cpp diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors