clk: keystone: add support for post divider register for main pll
authorMurali Karicheri <m-karicheri2@ti.com>
Fri, 29 May 2015 16:04:12 +0000 (12:04 -0400)
committerMichael Turquette <mturquette@baylibre.com>
Thu, 18 Jun 2015 22:36:33 +0000 (15:36 -0700)
commit02fdfd708fd252a778709beb6c65d5e7360341ac
tree1628c7d5e62c8626b2cba578ae1aac20fde1dd73
parent91990d213ca06fdecca19e10514ebec7c89ddca9
clk: keystone: add support for post divider register for main pll

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Documentation/devicetree/bindings/clock/keystone-pll.txt
drivers/clk/keystone/pll.c