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(parent: 6a224c3) | patch
AMDGPU/SI: Set DwarfRegNum
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 31 Jul 2015 01:12:10 +0000 (01:12 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 31 Jul 2015 01:12:10 +0000 (01:12 +0000)
commit01e2215a94ac1db09c970a0ae09ff2790b72c981
treef9deb4ed9ac0bcdde9eb37b9d9e413c6f1d6338ftree | snapshot
parent6a224c30a5d358305e6cfda1a62a78f658baa943commit | diff
AMDGPU/SI: Set DwarfRegNum

This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243723 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIRegisterInfo.td diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors