X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FSubtargetEmitter.cpp;h=e5c62fa13751bc59fe12967c5271c555e0487034;hb=bccc647eaade1acd96d43150d445201f9e30aa26;hp=0d36c4fd4684278f4333f5d51d08a037476378ad;hpb=6982bdd1193551e65effa3737f2a29d55e7901a5;p=oota-llvm.git diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 0d36c4fd468..e5c62fa1375 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -11,8 +11,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "subtarget-emitter" - #include "CodeGenTarget.h" #include "CodeGenSchedule.h" #include "llvm/ADT/STLExtras.h" @@ -29,6 +27,8 @@ #include using namespace llvm; +#define DEBUG_TYPE "subtarget-emitter" + namespace { class SubtargetEmitter { // Each processor has a SchedClassDesc table with an entry for each SchedClass. @@ -128,42 +128,29 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS, OS << "namespace " << Target << " {\n"; - // For bit flag enumerations with more than 32 items, emit constants. - // Emit an enum for everything else. - if (isBits && N > 32) { - // For each record - for (unsigned i = 0; i < N; i++) { - // Next record - Record *Def = DefList[i]; + // Open enumeration. Use a 64-bit underlying type. + OS << "enum : uint64_t {\n"; - // Get and emit name and expression (1 << i) - OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n"; - } - } else { - // Open enumeration - OS << "enum {\n"; - - // For each record - for (unsigned i = 0; i < N;) { - // Next record - Record *Def = DefList[i]; - - // Get and emit name - OS << " " << Def->getName(); + // For each record + for (unsigned i = 0; i < N;) { + // Next record + Record *Def = DefList[i]; - // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1ULL << " << i; + // Get and emit name + OS << " " << Def->getName(); - // Depending on 'if more in the list' emit comma - if (++i < N) OS << ","; + // If bit flags then emit expression (1 << i) + if (isBits) OS << " = " << " 1ULL << " << i; - OS << "\n"; - } + // Depending on 'if more in the list' emit comma + if (++i < N) OS << ","; - // Close enumeration - OS << "};\n"; + OS << "\n"; } + // Close enumeration + OS << "};\n"; + OS << "}\n"; } @@ -386,7 +373,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS, for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), PE = SchedModels.procModelEnd(); PI != PE; ++PI) { - if (!ItinsDefSet.insert(PI->ItinsDef)) + if (!ItinsDefSet.insert(PI->ItinsDef).second) continue; std::vector FUs = PI->ItinsDef->getValueAsListOfDefs("FU"); @@ -404,7 +391,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS, OS << "}\n"; std::vector BPs = PI->ItinsDef->getValueAsListOfDefs("BP"); - if (BPs.size()) { + if (!BPs.empty()) { OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name << "\"\n" << "namespace " << Name << "Bypass {\n"; @@ -565,7 +552,7 @@ EmitItineraries(raw_ostream &OS, PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) { Record *ItinsDef = PI->ItinsDef; - if (!ItinsDefSet.insert(ItinsDef)) + if (!ItinsDefSet.insert(ItinsDef).second) continue; // Get processor itinerary name @@ -575,12 +562,13 @@ EmitItineraries(raw_ostream &OS, assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator"); std::vector &ItinList = *ProcItinListsIter; + // Empty itineraries aren't referenced anywhere in the tablegen output + // so don't emit them. + if (ItinList.empty()) + continue; + OS << "\n"; OS << "static const llvm::InstrItinerary "; - if (ItinList.empty()) { - OS << '*' << Name << " = 0;\n"; - continue; - } // Begin processor itinerary table OS << Name << "[] = {\n"; @@ -631,19 +619,14 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { Record *PRDef = ProcModel.ProcResourceDefs[i]; - Record *SuperDef = 0; + Record *SuperDef = nullptr; unsigned SuperIdx = 0; unsigned NumUnits = 0; - bool IsBuffered = true; + int BufferSize = PRDef->getValueAsInt("BufferSize"); if (PRDef->isSubClassOf("ProcResGroup")) { RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end(); RUI != RUE; ++RUI) { - if (!NumUnits) - IsBuffered = (*RUI)->getValueAsBit("Buffered"); - else if(IsBuffered != (*RUI)->getValueAsBit("Buffered")) - PrintFatalError(PRDef->getLoc(), - "Mixing buffered and unbuffered resources."); NumUnits += (*RUI)->getValueAsInt("NumUnits"); } } @@ -655,7 +638,6 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, SuperIdx = ProcModel.getProcResourceIdx(SuperDef); } NumUnits = PRDef->getValueAsInt("NumUnits"); - IsBuffered = PRDef->getValueAsBit("Buffered"); } // Emit the ProcResourceDesc if (i+1 == e) @@ -664,7 +646,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, if (PRDef->getName().size() < 15) OS.indent(15 - PRDef->getName().size()); OS << NumUnits << ", " << SuperIdx << ", " - << IsBuffered << "}" << Sep << " // #" << i+1; + << BufferSize << "}" << Sep << " // #" << i+1; if (SuperDef) OS << ", Super=" << SuperDef->getName(); OS << "\n"; @@ -682,7 +664,7 @@ Record *SubtargetEmitter::FindWriteResources( if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) return SchedWrite.TheDef; - Record *AliasDef = 0; + Record *AliasDef = nullptr; for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end(); AI != AE; ++AI) { const CodeGenSchedRW &AliasRW = @@ -702,7 +684,7 @@ Record *SubtargetEmitter::FindWriteResources( return AliasDef; // Check this processor's list of write resources. - Record *ResDef = 0; + Record *ResDef = nullptr; for (RecIter WRI = ProcModel.WriteResDefs.begin(), WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) { if (!(*WRI)->isSubClassOf("WriteRes")) @@ -736,7 +718,7 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, return SchedRead.TheDef; // Check this processor's list of aliases for SchedRead. - Record *AliasDef = 0; + Record *AliasDef = nullptr; for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end(); AI != AE; ++AI) { const CodeGenSchedRW &AliasRW = @@ -756,7 +738,7 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, return AliasDef; // Check this processor's ReadAdvanceList. - Record *ResDef = 0; + Record *ResDef = nullptr; for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(), RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) { if (!(*RAI)->isSubClassOf("ReadAdvance")) @@ -782,29 +764,38 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, } // Expand an explicit list of processor resources into a full list of implied -// resource groups that cover them. -// -// FIXME: Effectively consider a super-resource a group that include all of its -// subresources to allow mixing and matching super-resources and groups. -// -// FIXME: Warn if two overlapping groups don't have a common supergroup. +// resource groups and super resources that cover them. void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, std::vector &Cycles, - const CodeGenProcModel &ProcModel) { + const CodeGenProcModel &PM) { // Default to 1 resource cycle. Cycles.resize(PRVec.size(), 1); for (unsigned i = 0, e = PRVec.size(); i != e; ++i) { + Record *PRDef = PRVec[i]; RecVec SubResources; - if (PRVec[i]->isSubClassOf("ProcResGroup")) { - SubResources = PRVec[i]->getValueAsListOfDefs("Resources"); - } + if (PRDef->isSubClassOf("ProcResGroup")) + SubResources = PRDef->getValueAsListOfDefs("Resources"); else { - SubResources.push_back(PRVec[i]); + SubResources.push_back(PRDef); + PRDef = SchedModels.findProcResUnits(PRVec[i], PM); + for (Record *SubDef = PRDef; + SubDef->getValueInit("Super")->isComplete();) { + if (SubDef->isSubClassOf("ProcResGroup")) { + // Disallow this for simplicitly. + PrintFatalError(SubDef->getLoc(), "Processor resource group " + " cannot be a super resources."); + } + Record *SuperDef = + SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM); + PRVec.push_back(SuperDef); + Cycles.push_back(Cycles[i]); + SubDef = SuperDef; + } } - for (RecIter PRI = ProcModel.ProcResourceDefs.begin(), - PRE = ProcModel.ProcResourceDefs.end(); + for (RecIter PRI = PM.ProcResourceDefs.begin(), + PRE = PM.ProcResourceDefs.end(); PRI != PRE; ++PRI) { - if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup")) + if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup")) continue; RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources"); RecIter SubI = SubResources.begin(), SubE = SubResources.end(); @@ -881,7 +872,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, if (!SCI->InstRWs.empty()) { // This class has a default ReadWrite list which can be overriden by // InstRW definitions. - Record *RWDef = 0; + Record *RWDef = nullptr; for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end(); RWI != RWE; ++RWI) { Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel"); @@ -1189,13 +1180,22 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { // Begin processor itinerary properties OS << "\n"; - OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n"; + OS << "static const llvm::MCSchedModel " << PI->ModelName << " = {\n"; EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ','); - EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ','); + EmitProcessorProp(OS, PI->ModelDef, "MicroOpBufferSize", ','); + EmitProcessorProp(OS, PI->ModelDef, "LoopMicroOpBufferSize", ','); EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); - EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ','); EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ','); + + OS << " " << (bool)(PI->ModelDef ? + PI->ModelDef->getValueAsBit("PostRAScheduler") : 0) + << ", // " << "PostRAScheduler\n"; + + OS << " " << (bool)(PI->ModelDef ? + PI->ModelDef->getValueAsBit("CompleteModel") : 0) + << ", // " << "CompleteModel\n"; + OS << " " << PI->Index << ", // Processor ID\n"; if (PI->hasInstrSchedModel()) OS << " " << PI->ModelName << "ProcResources" << ",\n" @@ -1205,10 +1205,10 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { - SchedModels.schedClassBegin()) << ",\n"; else OS << " 0, 0, 0, 0, // No instruction-level machine model.\n"; - if (SchedModels.hasItineraries()) - OS << " " << PI->ItinsDef->getName() << ");\n"; + if (PI->hasItineraries()) + OS << " " << PI->ItinsDef->getName() << "};\n"; else - OS << " 0); // No Itinerary\n"; + OS << " nullptr}; // No Itinerary\n"; } } @@ -1331,11 +1331,11 @@ void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName, for (std::vector::const_iterator TI = SC.Transitions.begin(), TE = SC.Transitions.end(); TI != TE; ++TI) { - OS << " if ("; if (*PI != 0 && !std::count(TI->ProcIndices.begin(), TI->ProcIndices.end(), *PI)) { continue; } + OS << " if ("; for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end(); RI != RE; ++RI) { if (RI != TI->PredTerm.begin()) @@ -1447,11 +1447,11 @@ void SubtargetEmitter::run(raw_ostream &OS) { if (NumFeatures) OS << Target << "FeatureKV, "; else - OS << "0, "; + OS << "None, "; if (NumProcs) OS << Target << "SubTypeKV, "; else - OS << "0, "; + OS << "None, "; OS << '\n'; OS.indent(22); OS << Target << "ProcSchedKV, " << Target << "WriteProcResTable, " @@ -1461,10 +1461,10 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << '\n'; OS.indent(22); OS << Target << "Stages, " << Target << "OperandCycles, " - << Target << "ForwardingPaths, "; + << Target << "ForwardingPaths"; } else - OS << "0, 0, 0, "; - OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; + OS << "0, 0, 0"; + OS << ");\n}\n\n"; OS << "} // End llvm namespace \n"; @@ -1491,7 +1491,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { << "StringRef FS);\n" << "public:\n" << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI," - << " const TargetSchedModel *SchedModel) const;\n" + << " const TargetSchedModel *SchedModel) const override;\n" << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" << " const;\n" << "};\n"; @@ -1525,13 +1525,13 @@ void SubtargetEmitter::run(raw_ostream &OS) { << " : TargetSubtargetInfo() {\n" << " InitMCSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) - OS << Target << "FeatureKV, "; + OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), "; else - OS << "0, "; + OS << "None, "; if (NumProcs) - OS << Target << "SubTypeKV, "; + OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), "; else - OS << "0, "; + OS << "None, "; OS << '\n'; OS.indent(22); OS << Target << "ProcSchedKV, " << Target << "WriteProcResTable, " @@ -1541,10 +1541,10 @@ void SubtargetEmitter::run(raw_ostream &OS) { if (SchedModels.hasItineraries()) { OS << Target << "Stages, " << Target << "OperandCycles, " - << Target << "ForwardingPaths, "; + << Target << "ForwardingPaths"; } else - OS << "0, 0, 0, "; - OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; + OS << "0, 0, 0"; + OS << ");\n}\n\n"; EmitSchedModelHelpers(ClassName, OS);