X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=156c145540746b1191b2058280720a9613fe9caf;hb=6e032942cf58d1c41f88609a1cec74eb74940ecd;hp=96399a4d0525108053cd428bc1dc55b8f4d70e2f;hpb=b83ff84193d44bb9aa75e1264ffaff55f468a303;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 96399a4d052..156c1455407 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -38,7 +38,10 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { OS << "enum {\n NoRegister,\n"; for (unsigned i = 0, e = Registers.size(); i != e; ++i) - OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; + OS << " " << Registers[i].getName() << " = " << + Registers[i].EnumValue << ",\n"; + assert(Registers.size() == Registers[Registers.size()-1].EnumValue && + "Register enum value mismatch!"); OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; OS << "};\n"; if (!Namespace.empty()) @@ -53,7 +56,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { OS << "enum {\n NoSubRegister,\n"; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; - OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n"; + OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; OS << "};\n"; if (!Namespace.empty()) OS << "}\n"; @@ -77,6 +80,8 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" << " virtual bool needsStackRealignment(const MachineFunction &) const\n" << " { return false; }\n" @@ -91,7 +96,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace << " { // Register classes\n"; - + OS << " enum {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; @@ -169,7 +174,7 @@ struct RegisterMaps { typedef std::map SubRegMaps; SubRegMaps SubReg; - SubRegMap &inferSubRegIndices(Record *Reg); + SubRegMap &inferSubRegIndices(Record *Reg, CodeGenTarget &); // Composite SubRegIndex instances. // Map (SubRegIndex,SubRegIndex) -> SubRegIndex @@ -182,7 +187,8 @@ struct RegisterMaps { }; // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion. -RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) { +RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg, + CodeGenTarget &Target) { SubRegMap &SRM = SubReg[Reg]; if (!SRM.empty()) return SRM; @@ -196,7 +202,7 @@ RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) { if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second) throw "SubRegIndex " + Indices[i]->getName() + " appears twice in Register " + Reg->getName(); - inferSubRegIndices(SubRegs[i]); + inferSubRegIndices(SubRegs[i], Target); } // Keep track of inherited subregs and how they can be reached. @@ -245,18 +251,17 @@ RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) { Orphans.erase(R2); } - // Now, Orphans contains the inherited subregisters without a direct index. - if (!Orphans.empty()) { - errs() << "Error: Register " << getQualifiedName(Reg) - << " inherited subregisters without an index:\n"; - for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e; - ++i) { - errs() << " " << getQualifiedName(i->first) - << " = " << i->second.first->getName() - << ", " << i->second.second->getName() << "\n"; - } - abort(); + // Now Orphans contains the inherited subregisters without a direct index. + // Create inferred indexes for all missing entries. + for (OrphanMap::iterator I = Orphans.begin(), E = Orphans.end(); I != E; + ++I) { + Record *&Comp = Composite[I->second]; + if (!Comp) + Comp = Target.createSubRegIndex(I->second.first->getName() + "_then_" + + I->second.second->getName()); + SRM[Comp] = I->first; } + return SRM; } @@ -290,14 +295,13 @@ void RegisterMaps::computeComposites() { if (i1d->second == Reg3) { std::pair Ins = Composite.insert(std::make_pair(IdxPair, i1d->first)); - // Conflicting composition? + // Conflicting composition? Emit a warning but allow it. if (!Ins.second && Ins.first->second != i1d->first) { - errs() << "Error: SubRegIndex " << getQualifiedName(Idx1) + errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1) << " and " << getQualifiedName(IdxPair.second) << " compose ambiguously as " << getQualifiedName(Ins.first->second) << " or " << getQualifiedName(i1d->first) << "\n"; - abort(); } } } @@ -358,7 +362,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - + // Emit the register list now. OS << " // " << Name << " Register Class...\n" << " static const unsigned " << Name @@ -376,12 +380,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Emit the ValueType arrays for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = RegisterClasses[rc]; - + // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName() + "VTs"; - + // Emit the register list now. - OS << " // " << Name + OS << " // " << Name << " Register Class Value Types...\n" << " static const EVT " << Name << "[] = {\n "; @@ -390,7 +394,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << "MVT::Other\n };\n\n"; } OS << "} // end anonymous namespace\n\n"; - + // Now that all of the structs have been emitted, emit the instances. if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace @@ -398,7 +402,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) OS << " " << RegisterClasses[i].getName() << "Class\t" << RegisterClasses[i].getName() << "RegClass;\n"; - + std::map > SuperClassMap; std::map > SuperRegClassMap; OS << "\n"; @@ -488,7 +492,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - OS << " // " << Name + OS << " // " << Name << " Register Class sub-classes...\n" << " static const TargetRegisterClass* const " << Name << "Subclasses[] = {\n "; @@ -500,7 +504,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Sub-classes are used to determine if a virtual register can be used // as an instruction operand, or if it must be copied first. if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; - + if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; Empty = false; @@ -524,7 +528,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - OS << " // " << Name + OS << " // " << Name << " Register Class super-classes...\n" << " static const TargetRegisterClass* const " << Name << "Superclasses[] = {\n "; @@ -538,7 +542,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; + Empty = false; } } @@ -550,7 +554,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; OS << RC.MethodBodies << "\n"; - OS << RC.getName() << "Class::" << RC.getName() + OS << RC.getName() << "Class::" << RC.getName() << "Class() : TargetRegisterClass(" << RC.getName() + "RegClassID" << ", " << '\"' << RC.getName() << "\", " @@ -567,7 +571,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; } - + OS << "}\n"; } @@ -584,7 +588,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { std::map, LessRecord> RegisterAliases; typedef std::map, LessRecord> DwarfRegNumsMapTy; DwarfRegNumsMapTy DwarfRegNums; - + const std::vector &Regs = Target.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -623,7 +627,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegisterAliases); } } - + // Print the SubregHashTable, a simple quadratically probed // hash table for determining if a register is a subregister // of another register. @@ -633,13 +637,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); } - + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); - + unsigned hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set::iterator I = RegisterSubRegs[R].begin(), @@ -654,26 +658,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { SubregHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (SubregHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + SubregHashTable[index*2] = i; SubregHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (SubregHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned SubregHashTable[] = { "; for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (SubregHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; @@ -681,7 +685,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = SubregHashTableSize*2-2; if (SubregHashTable[Idx] != ~0U) { OS << " " @@ -690,14 +694,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned SubregHashTableSize = " << SubregHashTableSize << ";\n"; } else { OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" << " const unsigned SubregHashTableSize = 1;\n"; } - + delete [] SubregHashTable; @@ -709,13 +713,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumAliases += RegisterAliases[Regs[i].TheDef].size(); } - + unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); - + hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set::iterator I = RegisterAliases[R].begin(), @@ -730,26 +734,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { AliasesHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (AliasesHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + AliasesHashTable[index*2] = i; AliasesHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (AliasesHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned AliasesHashTable[] = { "; for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (AliasesHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; @@ -757,7 +761,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = AliasesHashTableSize*2-2; if (AliasesHashTable[Idx] != ~0U) { OS << " " @@ -766,14 +770,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned AliasesHashTableSize = " << AliasesHashTableSize << ";\n"; } else { OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" << " const unsigned AliasesHashTableSize = 1;\n"; } - + delete [] AliasesHashTable; if (!RegisterAliases.empty()) @@ -838,7 +842,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -851,12 +855,20 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { else OS << "Empty_SubRegsSet,\t"; if (!RegisterSuperRegs[Reg.TheDef].empty()) - OS << Reg.getName() << "_SuperRegsSet },\n"; + OS << Reg.getName() << "_SuperRegsSet,\t"; else - OS << "Empty_SuperRegsSet },\n"; + OS << "Empty_SuperRegsSet,\t"; + OS << Reg.CostPerUse << " },\n"; } OS << " };\n"; // End of register descriptors... + // Calculate the mapping of subregister+index pairs to physical registers. + // This will also create further anonymous indexes. + unsigned NamedIndices = Target.getSubRegIndices().size(); + RegisterMaps RegMaps; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) + RegMaps.inferSubRegIndices(Regs[i].TheDef, Target); + // Emit SubRegIndex names, skipping 0 const std::vector SubRegIndices = Target.getSubRegIndices(); OS << "\n const char *const SubRegIndexTable[] = { \""; @@ -866,13 +878,21 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << "\", \""; } OS << "\" };\n\n"; + + // Emit names of the anonymus subreg indexes. + if (SubRegIndices.size() > NamedIndices) { + OS << " enum {"; + for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { + OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; + if (i+1 != e) + OS << ','; + } + OS << "\n };\n\n"; + } OS << "}\n\n"; // End of anonymous namespace... std::string ClassName = Target.getName() + "GenRegisterInfo"; - // Calculate the mapping of subregister+index pairs to physical registers. - RegisterMaps RegMaps; - // Emit the subregister + index mapping function based on the information // calculated above. OS << "unsigned " << ClassName @@ -880,7 +900,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " switch (RegNo) {\n" << " default:\n return 0;\n"; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef); + RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef]; if (SRM.empty()) continue; OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; @@ -966,11 +986,49 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } // Now we know maximal length of number list. Append -1's, where needed - for (DwarfRegNumsMapTy::iterator + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); + // Emit reverse information about the dwarf register numbers. + OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const {\n" + << " switch (Flavour) {\n" + << " default:\n" + << " assert(0 && \"Unknown DWARF flavour\");\n" + << " return -1;\n"; + + for (unsigned i = 0, e = maxLength; i != e; ++i) { + OS << " case " << i << ":\n" + << " switch (DwarfRegNum) {\n" + << " default:\n" + << " assert(0 && \"Invalid DwarfRegNum\");\n" + << " return -1;\n"; + + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { + int DwarfRegNo = I->second[i]; + if (DwarfRegNo >= 0) + OS << " case " << DwarfRegNo << ":\n" + << " return " << getQualifiedName(I->first) << ";\n"; + } + OS << " };\n"; + } + + OS << " };\n}\n\n"; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record *Reg = Regs[i].TheDef; + const RecordVal *V = Reg->getValue("DwarfAlias"); + if (!V || !V->getValue()) + continue; + + DefInit *DI = dynamic_cast(V->getValue()); + Record *Alias = DI->getDef(); + DwarfRegNums[Reg] = DwarfRegNums[Alias]; + } + // Emit information about the dwarf register numbers. OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const {\n" @@ -978,31 +1036,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " default:\n" << " assert(0 && \"Unknown DWARF flavour\");\n" << " return -1;\n"; - + for (unsigned i = 0, e = maxLength; i != e; ++i) { OS << " case " << i << ":\n" << " switch (RegNum) {\n" << " default:\n" << " assert(0 && \"Invalid RegNum\");\n" << " return -1;\n"; - + // Sort by name to get a stable order. - - for (DwarfRegNumsMapTy::iterator + + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { int RegNo = I->second[i]; - if (RegNo != -2) - OS << " case " << getQualifiedName(I->first) << ":\n" - << " return " << RegNo << ";\n"; - else - OS << " case " << getQualifiedName(I->first) << ":\n" - << " assert(0 && \"Invalid register for this mode\");\n" - << " return -1;\n"; + OS << " case " << getQualifiedName(I->first) << ":\n" + << " return " << RegNo << ";\n"; } OS << " };\n"; } - + OS << " };\n}\n\n"; OS << "} // End llvm namespace \n";