X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=c29f5c48bfa5adebe336e43c31a69dbd624356db;hb=1a6c683315bd88dea19b97a8752c0b8cc43e4285;hp=ad043bdc1049ae96d7a0e200aee18730d493f86d;hpb=719c2fc97f7dbf2fdc3743f2324a33c02cbb8b0c;p=oota-llvm.git diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index ad043bdc104..c29f5c48bfa 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -16,72 +16,130 @@ #include "CodeGenTarget.h" #include "Record.h" #include +#include using namespace llvm; -// runEnums - Print out enum values for all of the instructions. -void InstrInfoEmitter::runEnums(std::ostream &OS) { - EmitSourceFileHeader("Target Instruction Enum Values", OS); - OS << "namespace llvm {\n\n"; - - CodeGenTarget Target; - - // We must emit the PHI opcode first... - Record *InstrInfo = Target.getInstructionSet(); - - std::string Namespace = Target.inst_begin()->second.Namespace; - - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << " enum {\n"; - - std::vector NumberedInstructions; - Target.getInstructionsByEnumValue(NumberedInstructions); - - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - OS << " " << NumberedInstructions[i]->TheDef->getName() - << ", \t// " << i << "\n"; - } - OS << " INSTRUCTION_LIST_END\n"; - OS << " };\n"; - if (!Namespace.empty()) - OS << "}\n"; - OS << "} // End llvm namespace \n"; -} - -void InstrInfoEmitter::printDefList(const std::vector &Uses, - unsigned Num, std::ostream &OS) const { +static void PrintDefList(const std::vector &Uses, + unsigned Num, std::ostream &OS) { OS << "static const unsigned ImplicitList" << Num << "[] = { "; for (unsigned i = 0, e = Uses.size(); i != e; ++i) OS << getQualifiedName(Uses[i]) << ", "; OS << "0 };\n"; } -static std::vector GetOperandInfo(const CodeGenInstruction &Inst) { - std::vector Result; - if (Inst.hasVariableNumberOfOperands) - return Result; // No info for variable operand instrs. +//===----------------------------------------------------------------------===// +// Instruction Itinerary Information. +//===----------------------------------------------------------------------===// + +struct RecordNameComparator { + bool operator()(const Record *Rec1, const Record *Rec2) const { + return Rec1->getName() < Rec2->getName(); + } +}; + +void InstrInfoEmitter::GatherItinClasses() { + std::vector DefList = + Records.getAllDerivedDefinitions("InstrItinClass"); + std::sort(DefList.begin(), DefList.end(), RecordNameComparator()); + + for (unsigned i = 0, N = DefList.size(); i < N; i++) + ItinClassMap[DefList[i]->getName()] = i; +} + +unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { + return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; +} + +//===----------------------------------------------------------------------===// +// Operand Info Emission. +//===----------------------------------------------------------------------===// +std::vector +InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { + std::vector Result; + for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { - if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) { - Result.push_back(Inst.OperandList[i].Rec); + // Handle aggregate operands and normal operands the same way by expanding + // either case into a list of operands for this op. + std::vector OperandList; + + // This might be a multiple operand thing. Targets like X86 have + // registers in their multi-operand operands. It may also be an anonymous + // operand, which has a single operand, but no declared class for the + // operand. + DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; + + if (!MIOI || MIOI->getNumArgs() == 0) { + // Single, anonymous, operand. + OperandList.push_back(Inst.OperandList[i]); } else { - // This might be a multiple operand thing. - // Targets like X86 have registers in their multi-operand operands. - DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; - unsigned NumDefs = MIOI->getNumArgs(); for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { - if (NumDefs <= j) { - Result.push_back(0); - } else { - DefInit *Def = dynamic_cast(MIOI->getArg(j)); - Result.push_back(Def ? Def->getDef() : 0); - } + OperandList.push_back(Inst.OperandList[i]); + + Record *OpR = dynamic_cast(MIOI->getArg(j))->getDef(); + OperandList.back().Rec = OpR; } } + + for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { + Record *OpR = OperandList[j].Rec; + std::string Res; + + if (OpR->isSubClassOf("RegisterClass")) + Res += getQualifiedName(OpR) + "RegClassID, "; + else + Res += "0, "; + // Fill in applicable flags. + Res += "0"; + + // Ptr value whose register class is resolved via callback. + if (OpR->getName() == "ptr_rc") + Res += "|(1<isSubClassOf("PredicateOperand")) + Res += "|(1<isSubClassOf("OptionalDefOperand")) + Res += "|(1<()] = ++OperandListNum; + + OS << "\n"; + const CodeGenTarget &Target = CDP.getTargetInfo(); + for (CodeGenTarget::inst_iterator II = Target.inst_begin(), + E = Target.inst_end(); II != E; ++II) { + std::vector OperandInfo = GetOperandInfo(II->second); + unsigned &N = OperandInfoIDs[OperandInfo]; + if (N != 0) continue; + + N = ++OperandListNum; + OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; + for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) + OS << "{ " << OperandInfo[i] << " }, "; + OS << "};\n"; + } +} + +//===----------------------------------------------------------------------===// +// Main Output. +//===----------------------------------------------------------------------===// // run - Emit the main instruction description records for the target... void InstrInfoEmitter::run(std::ostream &OS) { @@ -90,13 +148,10 @@ void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); OS << "namespace llvm {\n\n"; - CodeGenTarget Target; + CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); - // Emit empty implicit uses and defs lists - OS << "static const unsigned EmptyImpList[] = { 0 };\n"; - // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; @@ -108,51 +163,30 @@ void InstrInfoEmitter::run(std::ostream &OS) { std::vector Uses = Inst->getValueAsListOfDefs("Uses"); if (!Uses.empty()) { unsigned &IL = EmittedLists[Uses]; - if (!IL) printDefList(Uses, IL = ++ListNumber, OS); + if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { unsigned &IL = EmittedLists[Defs]; - if (!IL) printDefList(Defs, IL = ++ListNumber, OS); + if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } } - std::map, unsigned> OperandInfosEmitted; - unsigned OperandListNum = 0; - OperandInfosEmitted[std::vector()] = ++OperandListNum; + OperandInfoMapTy OperandInfoIDs; // Emit all of the operand info records. - OS << "\n"; - for (CodeGenTarget::inst_iterator II = Target.inst_begin(), - E = Target.inst_end(); II != E; ++II) { - std::vector OperandInfo = GetOperandInfo(II->second); - unsigned &N = OperandInfosEmitted[OperandInfo]; - if (N == 0) { - N = ++OperandListNum; - OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; - for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) { - Record *RC = OperandInfo[i]; - // FIXME: We only care about register operands for now. - if (RC && RC->isSubClassOf("RegisterClass")) { - OS << "{ &" << getQualifiedName(RC) << "RegClass }, "; - } else { - OS << "{ 0 }, "; - } - } - OS << "};\n"; - } - } + EmitOperandInfo(OS, OperandInfoIDs); - // Emit all of the TargetInstrDescriptor records in their ENUM ordering. + // Emit all of the TargetInstrDesc records in their ENUM ordering. // - OS << "\nstatic const TargetInstrDescriptor " << TargetName + OS << "\nstatic const TargetInstrDesc " << TargetName << "Insts[] = {\n"; std::vector NumberedInstructions; Target.getInstructionsByEnumValue(NumberedInstructions); for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - OperandInfosEmitted, OS); + OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -160,44 +194,41 @@ void InstrInfoEmitter::run(std::ostream &OS) { void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, - std::map, unsigned> &OpInfo, + const OperandInfoMapTy &OpInfo, std::ostream &OS) { - int NumOperands; - if (Inst.hasVariableNumberOfOperands) - NumOperands = -1; - else if (!Inst.OperandList.empty()) + int MinOperands = 0; + if (!Inst.OperandList.empty()) // Each logical operand can be multiple MI operands. - NumOperands = Inst.OperandList.back().MIOperandNo + + MinOperands = Inst.OperandList.back().MIOperandNo + Inst.OperandList.back().MINumOperands; - else - NumOperands = 0; - - OS << " { \""; - if (Inst.Name.empty()) - OS << Inst.TheDef->getName(); - else - OS << Inst.Name; - - unsigned ItinClass = !IsItineraries ? 0 : - ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName()); - - OS << "\",\t" << NumOperands << ", " << ItinClass - << ", 0"; + + OS << " { "; + OS << Num << ",\t" << MinOperands << ",\t" + << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) + << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|M_RET_FLAG"; - if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; - if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; - if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; - if (Inst.isCall) OS << "|M_CALL_FLAG"; - if (Inst.isLoad) OS << "|M_LOAD_FLAG"; - if (Inst.isStore) OS << "|M_STORE_FLAG"; - if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; - if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; - if (Inst.isCommutable) OS << "|M_COMMUTABLE"; - if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; + if (Inst.isReturn) OS << "|(1< UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); if (UseList.empty()) - OS << "EmptyImpList, "; + OS << "NULL, "; else OS << "ImplicitList" << EmittedLists[UseList] << ", "; std::vector DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); if (DefList.empty()) - OS << "EmptyImpList, "; + OS << "NULL, "; else OS << "ImplicitList" << EmittedLists[DefList] << ", "; // Emit the operand info. - std::vector OperandInfo = GetOperandInfo(Inst); + std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) OS << "0"; else - OS << "OperandInfo" << OpInfo[OperandInfo]; + OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } -struct LessRecord { - bool operator()(const Record *Rec1, const Record *Rec2) const { - return Rec1->getName() < Rec2->getName(); - } -}; -void InstrInfoEmitter::GatherItinClasses() { - std::vector DefList = - Records.getAllDerivedDefinitions("InstrItinClass"); - IsItineraries = !DefList.empty(); - - if (!IsItineraries) return; - - std::sort(DefList.begin(), DefList.end(), LessRecord()); - - for (unsigned i = 0, N = DefList.size(); i < N; i++) { - Record *Def = DefList[i]; - ItinClassMap[Def->getName()] = i; - } -} - -unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) { - return ItinClassMap[ItinName]; -} void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, IntInit *ShiftInt, std::ostream &OS) { @@ -269,7 +277,16 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, if (RV == 0 || RV->getValue() == 0) { // This isn't an error if this is a builtin instruction. - if (R->getName() != "PHI" && R->getName() != "INLINEASM") + if (R->getName() != "PHI" && + R->getName() != "INLINEASM" && + R->getName() != "DBG_LABEL" && + R->getName() != "EH_LABEL" && + R->getName() != "GC_LABEL" && + R->getName() != "DECLARE" && + R->getName() != "EXTRACT_SUBREG" && + R->getName() != "INSERT_SUBREG" && + R->getName() != "IMPLICIT_DEF" && + R->getName() != "SUBREG_TO_REG") throw R->getName() + " doesn't have a field named '" + Val->getValue() + "'!"; return;