X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=3706f2d0a76eb67cc517d0d53e4a2c7165604607;hb=88d2fa438a5b9feb7da77e4beeaa00944ae4168e;hp=d357f33f1a897913d7bdb4f773b97ea5dcd6424a;hpb=749c6f6b5ed301c84aac562e414486549d7b98eb;p=oota-llvm.git

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index d357f33f1a8..3706f2d0a76 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -14,13 +14,14 @@
 
 #include "InstrInfoEmitter.h"
 #include "CodeGenTarget.h"
-#include "Record.h"
+#include "StringToOffsetTable.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/ADT/StringExtras.h"
 #include <algorithm>
-#include <iostream>
 using namespace llvm;
 
 static void PrintDefList(const std::vector<Record*> &Uses,
-                         unsigned Num, std::ostream &OS) {
+                         unsigned Num, raw_ostream &OS) {
   OS << "static const unsigned ImplicitList" << Num << "[] = { ";
   for (unsigned i = 0, e = Uses.size(); i != e; ++i)
     OS << getQualifiedName(Uses[i]) << ", ";
@@ -31,20 +32,14 @@ static void PrintDefList(const std::vector<Record*> &Uses,
 // Instruction Itinerary Information.
 //===----------------------------------------------------------------------===//
 
-struct RecordNameComparator {
-  bool operator()(const Record *Rec1, const Record *Rec2) const {
-    return Rec1->getName() < Rec2->getName();
-  }
-};
-
 void InstrInfoEmitter::GatherItinClasses() {
   std::vector<Record*> DefList =
   Records.getAllDerivedDefinitions("InstrItinClass");
-  std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
-  
+  std::sort(DefList.begin(), DefList.end(), LessRecord());
+
   for (unsigned i = 0, N = DefList.size(); i < N; i++)
     ItinClassMap[DefList[i]->getName()] = i;
-}  
+}
 
 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
   return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
@@ -57,24 +52,24 @@ unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
 std::vector<std::string>
 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
   std::vector<std::string> Result;
-  
-  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
+
+  for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
     // Handle aggregate operands and normal operands the same way by expanding
     // either case into a list of operands for this op.
-    std::vector<CodeGenInstruction::OperandInfo> OperandList;
+    std::vector<CGIOperandList::OperandInfo> OperandList;
 
     // This might be a multiple operand thing.  Targets like X86 have
     // registers in their multi-operand operands.  It may also be an anonymous
     // operand, which has a single operand, but no declared class for the
     // operand.
-    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
-    
+    DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
+
     if (!MIOI || MIOI->getNumArgs() == 0) {
       // Single, anonymous, operand.
-      OperandList.push_back(Inst.OperandList[i]);
+      OperandList.push_back(Inst.Operands[i]);
     } else {
-      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
-        OperandList.push_back(Inst.OperandList[i]);
+      for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
+        OperandList.push_back(Inst.Operands[i]);
 
         Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
         OperandList.back().Rec = OpR;
@@ -84,30 +79,54 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
     for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
       Record *OpR = OperandList[j].Rec;
       std::string Res;
-      
+
+      if (OpR->isSubClassOf("RegisterOperand"))
+        OpR = OpR->getValueAsDef("RegClass");
       if (OpR->isSubClassOf("RegisterClass"))
         Res += getQualifiedName(OpR) + "RegClassID, ";
+      else if (OpR->isSubClassOf("PointerLikeRegClass"))
+        Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
       else
-        Res += "0, ";
+        // -1 means the operand does not have a fixed register class.
+        Res += "-1, ";
+
       // Fill in applicable flags.
       Res += "0";
-        
+
       // Ptr value whose register class is resolved via callback.
-      if (OpR->getName() == "ptr_rc")
-        Res += "|(1<<TOI::LookupPtrRegClass)";
+      if (OpR->isSubClassOf("PointerLikeRegClass"))
+        Res += "|(1<<MCOI::LookupPtrRegClass)";
 
       // Predicate operands.  Check to see if the original unexpanded operand
       // was of type PredicateOperand.
-      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
-        Res += "|(1<<TOI::Predicate)";
-        
+      if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
+        Res += "|(1<<MCOI::Predicate)";
+
       // Optional def operands.  Check to see if the original unexpanded operand
       // was of type OptionalDefOperand.
-      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
-        Res += "|(1<<TOI::OptionalDef)";
+      if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
+        Res += "|(1<<MCOI::OptionalDef)";
 
       // Fill in constraint info.
-      Res += ", " + Inst.OperandList[i].Constraints[j];
+      Res += ", ";
+
+      const CGIOperandList::ConstraintInfo &Constraint =
+        Inst.Operands[i].Constraints[j];
+      if (Constraint.isNone())
+        Res += "0";
+      else if (Constraint.isEarlyClobber())
+        Res += "(1 << MCOI::EARLY_CLOBBER)";
+      else {
+        assert(Constraint.isTied());
+        Res += "((" + utostr(Constraint.getTiedOperand()) +
+                    " << 16) | (1 << MCOI::TIED_TO))";
+      }
+
+      // Fill in operand type.
+      Res += ", MCOI::";
+      assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
+      Res += Inst.Operands[i].OperandType;
+
       Result.push_back(Res);
     }
   }
@@ -115,135 +134,57 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
   return Result;
 }
 
-void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS, 
+void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
                                        OperandInfoMapTy &OperandInfoIDs) {
   // ID #0 is for no operand info.
   unsigned OperandListNum = 0;
   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
-  
+
   OS << "\n";
   const CodeGenTarget &Target = CDP.getTargetInfo();
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
        E = Target.inst_end(); II != E; ++II) {
-    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
+    std::vector<std::string> OperandInfo = GetOperandInfo(**II);
     unsigned &N = OperandInfoIDs[OperandInfo];
     if (N != 0) continue;
-    
+
     N = ++OperandListNum;
-    OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+    OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
     for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
       OS << "{ " << OperandInfo[i] << " }, ";
     OS << "};\n";
   }
 }
 
-//===----------------------------------------------------------------------===//
-// Instruction Analysis
-//===----------------------------------------------------------------------===//
-
-class InstAnalyzer {
-  const CodeGenDAGPatterns &CDP;
-  bool &mayStore;
-  bool &isLoad;
-  bool &NeverHasSideEffects;
-public:
-  InstAnalyzer(const CodeGenDAGPatterns &cdp,
-               bool &maystore, bool &isload, bool &nhse)
-    : CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
-  }
-  
-  void Analyze(Record *InstRecord) {
-    const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
-    if (Pattern == 0) return;  // No pattern.
-    
-    // Assume there is no side-effect unless we see one.
-    NeverHasSideEffects = true;
-    
-    // FIXME: Assume only the first tree is the pattern. The others are clobber
-    // nodes.
-    AnalyzeNode(Pattern->getTree(0));
-  }
-  
-private:
-  void AnalyzeNode(const TreePatternNode *N) {
-    if (N->isLeaf()) {
-      return;
-    }
-
-    if (N->getOperator()->getName() != "set") {
-      // Get information about the SDNode for the operator.
-      const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
-      
-      // If node writes to memory, it obviously stores to memory.
-      if (OpInfo.hasProperty(SDNPMayStore)) {
-        mayStore = true;
-      } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
-        // If this is an intrinsic, analyze it.
-        if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
-          mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
-      }
-    }
-
-    for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
-      AnalyzeNode(N->getChild(i));
-  }
-  
-};
-
-void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, 
-                                        bool &mayStore, bool &isLoad, 
-                                        bool &NeverHasSideEffects) {
-  mayStore = isLoad = NeverHasSideEffects = false;
-  
-  InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
-
-  // InstAnalyzer only correctly analyzes mayStore so far.
-  if (Inst.mayStore) {  // If the .td file explicitly sets mayStore, use it.
-    // If we decided that this is a store from the pattern, then the .td file
-    // entry is redundant.
-    if (mayStore)
-      fprintf(stderr, 
-              "Warning: mayStore flag explicitly set on instruction '%s'"
-              " but flag already inferred from pattern.\n", 
-              Inst.TheDef->getName().c_str());
-    mayStore = true;
-  }
-
-  // These two override everything.
-  isLoad              = Inst.isSimpleLoad;
-  NeverHasSideEffects = Inst.neverHasSideEffects;
-
-#if 0
-  // If the .td file explicitly says there is no side effect, believe it.
-  if (Inst.neverHasSideEffects)
-    NeverHasSideEffects = true;
-#endif
-}
-
-
 //===----------------------------------------------------------------------===//
 // Main Output.
 //===----------------------------------------------------------------------===//
 
 // run - Emit the main instruction description records for the target...
-void InstrInfoEmitter::run(std::ostream &OS) {
+void InstrInfoEmitter::run(raw_ostream &OS) {
+  emitEnums(OS);
+
   GatherItinClasses();
 
   EmitSourceFileHeader("Target Instruction Descriptors", OS);
+
+  OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
+  OS << "#undef GET_INSTRINFO_MC_DESC\n";
+
   OS << "namespace llvm {\n\n";
 
-  CodeGenTarget Target;
+  CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
- 
+
   // Emit all of the instruction's implicit uses and defs.
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
          E = Target.inst_end(); II != E; ++II) {
-    Record *Inst = II->second.TheDef;
+    Record *Inst = (*II)->TheDef;
     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
     if (!Uses.empty()) {
       unsigned &IL = EmittedLists[Uses];
@@ -257,86 +198,138 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   }
 
   OperandInfoMapTy OperandInfoIDs;
-  
+
   // Emit all of the operand info records.
   EmitOperandInfo(OS, OperandInfoIDs);
-  
-  // Emit all of the TargetInstrDesc records in their ENUM ordering.
+
+  // Emit all of the MCInstrDesc records in their ENUM ordering.
   //
-  OS << "\nstatic const TargetInstrDesc " << TargetName
-     << "Insts[] = {\n";
-  std::vector<const CodeGenInstruction*> NumberedInstructions;
-  Target.getInstructionsByEnumValue(NumberedInstructions);
+  OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
+  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+    Target.getInstructionsByEnumValue();
 
   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
     emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
                OperandInfoIDs, OS);
-  OS << "};\n";
+  OS << "};\n\n";
+
+  OS << "extern const uint16_t " << TargetName <<"InstrNameIndices[] = {\n    ";
+  StringToOffsetTable StringTable;
+  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+    const CodeGenInstruction *Instr = NumberedInstructions[i];
+    unsigned Idx = StringTable.GetOrAddStringOffset(Instr->TheDef->getName());
+    assert(Idx <= 0xffff && "String offset too large to fit in table");
+    OS << Idx << "U, ";
+    if (i % 8 == 0)
+      OS << "\n    ";
+  }
+
+  OS << "\n};\n\n";
+
+  OS << "extern const char *const " << TargetName << "InstrNameData =\n";
+  StringTable.EmitString(OS);
+  OS << ";\n\n";
+
+  // MCInstrInfo initialization routine.
+  OS << "static inline void Init" << TargetName
+     << "MCInstrInfo(MCInstrInfo *II) {\n";
+  OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, "
+     << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
+     << NumberedInstructions.size() << ");\n}\n\n";
+
   OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
+
+  // Create a TargetInstrInfo subclass to hide the MC layer initialization.
+  OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
+  OS << "#undef GET_INSTRINFO_HEADER\n";
+
+  std::string ClassName = TargetName + "GenInstrInfo";
+  OS << "namespace llvm {\n";
+  OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
+     << "  explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
+     << "};\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_HEADER\n\n";
+
+  OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
+  OS << "#undef GET_INSTRINFO_CTOR\n";
+
+  OS << "namespace llvm {\n";
+  OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
+  OS << "extern const uint16_t " << TargetName << "InstrNameIndices[];\n";
+  OS << "extern const char *const " << TargetName << "InstrNameData;\n";
+  OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
+     << "  : TargetInstrInfoImpl(SO, DO) {\n"
+     << "  InitMCInstrInfo(" << TargetName << "Insts, "
+     << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
+     << NumberedInstructions.size() << ");\n}\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_CTOR\n\n";
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
                                   const OperandInfoMapTy &OpInfo,
-                                  std::ostream &OS) {
-  // Determine properties of the instruction from its pattern.
-  bool mayStore, isSimpleLoad, NeverHasSideEffects;
-  InferFromPattern(Inst, mayStore, isSimpleLoad, NeverHasSideEffects);
-  
-  if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
-    std::cerr << "error: Instruction '" << Inst.TheDef->getName()
-      << "' is marked with 'mayHaveSideEffects', but it can never have them!\n";
-    exit(1);
-  }
-  
+                                  raw_ostream &OS) {
   int MinOperands = 0;
-  if (!Inst.OperandList.empty())
+  if (!Inst.Operands.size() == 0)
     // Each logical operand can be multiple MI operands.
-    MinOperands = Inst.OperandList.back().MIOperandNo +
-                  Inst.OperandList.back().MINumOperands;
-  
+    MinOperands = Inst.Operands.back().MIOperandNo +
+                  Inst.Operands.back().MINumOperands;
+
   OS << "  { ";
   OS << Num << ",\t" << MinOperands << ",\t"
-     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
-     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
+     << Inst.Operands.NumDefs << ",\t"
+     << getItinClassNumber(Inst.TheDef) << ",\t"
+     << Inst.TheDef->getValueAsInt("Size") << ",\t0";
 
   // Emit all of the target indepedent flags...
-  if (Inst.isReturn)     OS << "|(1<<TID::Return)";
-  if (Inst.isBranch)     OS << "|(1<<TID::Branch)";
-  if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
-  if (Inst.isBarrier)    OS << "|(1<<TID::Barrier)";
-  if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
-  if (Inst.isCall)       OS << "|(1<<TID::Call)";
-  if (isSimpleLoad)      OS << "|(1<<TID::SimpleLoad)";
-  if (mayStore)          OS << "|(1<<TID::MayStore)";
-  if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
-  if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
-  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
-  if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
-  if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
-  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
-  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
-  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
-  if (Inst.usesCustomDAGSchedInserter)
-    OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
-  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
-  if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)";
-  if (NeverHasSideEffects)     OS << "|(1<<TID::NeverHasSideEffects)";
-  OS << ", 0";
+  if (Inst.isPseudo)           OS << "|(1<<MCID::Pseudo)";
+  if (Inst.isReturn)           OS << "|(1<<MCID::Return)";
+  if (Inst.isBranch)           OS << "|(1<<MCID::Branch)";
+  if (Inst.isIndirectBranch)   OS << "|(1<<MCID::IndirectBranch)";
+  if (Inst.isCompare)          OS << "|(1<<MCID::Compare)";
+  if (Inst.isMoveImm)          OS << "|(1<<MCID::MoveImm)";
+  if (Inst.isBitcast)          OS << "|(1<<MCID::Bitcast)";
+  if (Inst.isBarrier)          OS << "|(1<<MCID::Barrier)";
+  if (Inst.hasDelaySlot)       OS << "|(1<<MCID::DelaySlot)";
+  if (Inst.isCall)             OS << "|(1<<MCID::Call)";
+  if (Inst.canFoldAsLoad)      OS << "|(1<<MCID::FoldableAsLoad)";
+  if (Inst.mayLoad)            OS << "|(1<<MCID::MayLoad)";
+  if (Inst.mayStore)           OS << "|(1<<MCID::MayStore)";
+  if (Inst.isPredicable)       OS << "|(1<<MCID::Predicable)";
+  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
+  if (Inst.isCommutable)       OS << "|(1<<MCID::Commutable)";
+  if (Inst.isTerminator)       OS << "|(1<<MCID::Terminator)";
+  if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
+  if (Inst.isNotDuplicable)    OS << "|(1<<MCID::NotDuplicable)";
+  if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
+  if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
+  if (Inst.hasPostISelHook)    OS << "|(1<<MCID::HasPostISelHook)";
+  if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
+  if (Inst.hasSideEffects)     OS << "|(1<<MCID::UnmodeledSideEffects)";
+  if (Inst.isAsCheapAsAMove)   OS << "|(1<<MCID::CheapAsAMove)";
+  if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
+  if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
 
   // Emit all of the target-specific flags...
-  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
-  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
-  if (LI->getSize() != Shift->getSize())
-    throw "Lengths of " + InstrInfo->getName() +
-          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
-
-  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
-    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
-                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
-
-  OS << ", ";
+  BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
+  if (!TSF) throw "no TSFlags?";
+  uint64_t Value = 0;
+  for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
+    if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
+      Value |= uint64_t(Bit->getValue()) << i;
+    else
+      throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
+  }
+  OS << ", 0x";
+  OS.write_hex(Value);
+  OS << "ULL, ";
 
   // Emit the implicit uses and defs lists...
   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
@@ -357,59 +350,41 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
     OS << "0";
   else
     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
-  
+
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }
 
+// emitEnums - Print out enum values for all of the instructions.
+void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
+  EmitSourceFileHeader("Target Instruction Enum Values", OS);
+
+  OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
+  OS << "#undef GET_INSTRINFO_ENUM\n";
 
-void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
-                                        IntInit *ShiftInt, std::ostream &OS) {
-  if (Val == 0 || ShiftInt == 0)
-    throw std::string("Illegal value or shift amount in TargetInfo*!");
-  RecordVal *RV = R->getValue(Val->getValue());
-  int Shift = ShiftInt->getValue();
-
-  if (RV == 0 || RV->getValue() == 0) {
-    // This isn't an error if this is a builtin instruction.
-    if (R->getName() != "PHI" &&
-        R->getName() != "INLINEASM" &&
-        R->getName() != "LABEL" &&
-        R->getName() != "EXTRACT_SUBREG" &&
-        R->getName() != "INSERT_SUBREG")
-      throw R->getName() + " doesn't have a field named '" + 
-            Val->getValue() + "'!";
-    return;
+  OS << "namespace llvm {\n\n";
+
+  CodeGenTarget Target(Records);
+
+  // We must emit the PHI opcode first...
+  std::string Namespace = Target.getInstNamespace();
+  
+  if (Namespace.empty()) {
+    fprintf(stderr, "No instructions defined!\n");
+    exit(1);
   }
 
-  Init *Value = RV->getValue();
-  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
-    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
-    return;
-  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
-    // Convert the Bits to an integer to print...
-    Init *I = BI->convertInitializerTo(new IntRecTy());
-    if (I)
-      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
-        if (II->getValue()) {
-          if (Shift)
-            OS << "|(" << II->getValue() << "<<" << Shift << ")";
-          else
-            OS << "|" << II->getValue();
-        }
-        return;
-      }
+  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+    Target.getInstructionsByEnumValue();
 
-  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
-    if (II->getValue()) {
-      if (Shift)
-        OS << "|(" << II->getValue() << "<<" << Shift << ")";
-      else
-        OS << II->getValue();
-    }
-    return;
+  OS << "namespace " << Namespace << " {\n";
+  OS << "  enum {\n";
+  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+    OS << "    " << NumberedInstructions[i]->TheDef->getName()
+       << "\t= " << i << ",\n";
   }
+  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+  OS << "  };\n}\n";
+  OS << "} // End llvm namespace \n";
 
-  std::cerr << "Unhandled initializer: " << *Val << "\n";
-  throw "In record '" + R->getName() + "' for TSFlag emission.";
+  OS << "#endif // GET_INSTRINFO_ENUM\n\n";
 }
-