X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeGenTarget.h;h=d6458f41cf23bf8d35974cbd34c9e05952a520e1;hb=af73dfe6f1703aafa79f0c57ef2bd154be154686;hp=36b875993228d6203315ddc453624115c4fa4933;hpb=0fc71988900e600f3ef5b13d9682e2bbab92811d;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h index 36b87599322..d6458f41cf2 100644 --- a/utils/TableGen/CodeGenTarget.h +++ b/utils/TableGen/CodeGenTarget.h @@ -2,176 +2,212 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines wrappers for the Target class and related global // functionality. This makes it easier to access the data and provides a single -// place that needs to check it for validity. All of these classes throw -// exceptions on error conditions. +// place that needs to check it for validity. All of these classes abort +// on error conditions. // //===----------------------------------------------------------------------===// #ifndef CODEGEN_TARGET_H #define CODEGEN_TARGET_H -#include "CodeGenRegisters.h" #include "CodeGenInstruction.h" -#include -#include +#include "CodeGenRegisters.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/TableGen/Record.h" +#include namespace llvm { -class Record; -class RecordKeeper; struct CodeGenRegister; +class CodeGenSchedModels; +class CodeGenTarget; + +// SelectionDAG node properties. +// SDNPMemOperand: indicates that a node touches memory and therefore must +// have an associated memory operand that describes the access. +enum SDNP { + SDNPCommutative, + SDNPAssociative, + SDNPHasChain, + SDNPOutGlue, + SDNPInGlue, + SDNPOptInGlue, + SDNPMayLoad, + SDNPMayStore, + SDNPSideEffect, + SDNPMemOperand, + SDNPVariadic, + SDNPWantRoot, + SDNPWantParent +}; -/// getValueType - Return the MVT::ValueType that the specified TableGen record -/// corresponds to. -MVT::ValueType getValueType(Record *Rec); +/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// record corresponds to. +MVT::SimpleValueType getValueType(Record *Rec); -std::ostream &operator<<(std::ostream &OS, MVT::ValueType T); -std::string getName(MVT::ValueType T); -std::string getEnumName(MVT::ValueType T); +std::string getName(MVT::SimpleValueType T); +std::string getEnumName(MVT::SimpleValueType T); +/// getQualifiedName - Return the name of the specified record, with a +/// namespace qualifier if the record contains one. +std::string getQualifiedName(const Record *R); /// CodeGenTarget - This class corresponds to the Target class in the .td files. /// class CodeGenTarget { + RecordKeeper &Records; Record *TargetRec; - std::vector CalleeSavedRegisters; - MVT::ValueType PointerType; - - mutable std::map Instructions; - mutable std::vector Registers; - mutable std::vector RegisterClasses; - mutable std::vector LegalValueTypes; - void ReadRegisters() const; - void ReadRegisterClasses() const; + + mutable DenseMap Instructions; + mutable CodeGenRegBank *RegBank; + mutable std::vector RegAltNameIndices; + mutable SmallVector LegalValueTypes; + void ReadRegAltNameIndices() const; void ReadInstructions() const; void ReadLegalValueTypes() const; + + mutable CodeGenSchedModels *SchedModels; + + mutable std::vector InstrsByEnum; public: - CodeGenTarget(); + CodeGenTarget(RecordKeeper &Records); + ~CodeGenTarget(); Record *getTargetRecord() const { return TargetRec; } const std::string &getName() const; - const std::vector &getCalleeSavedRegisters() const { - return CalleeSavedRegisters; - } - - MVT::ValueType getPointerType() const { return PointerType; } + /// getInstNamespace - Return the target-specific instruction namespace. + /// + std::string getInstNamespace() const; /// getInstructionSet - Return the InstructionSet object. /// Record *getInstructionSet() const; + /// getAsmParser - Return the AssemblyParser definition for this target. + /// + Record *getAsmParser() const; + + /// getAsmParserVariant - Return the AssmblyParserVariant definition for + /// this target. + /// + Record *getAsmParserVariant(unsigned i) const; + + /// getAsmParserVariantCount - Return the AssmblyParserVariant definition + /// available for this target. + /// + unsigned getAsmParserVariantCount() const; + /// getAsmWriter - Return the AssemblyWriter definition for this target. /// Record *getAsmWriter() const; - const std::vector &getRegisters() const { - if (Registers.empty()) ReadRegisters(); - return Registers; - } + /// getRegBank - Return the register bank description. + CodeGenRegBank &getRegBank() const; - const std::vector &getRegisterClasses() const { - if (RegisterClasses.empty()) ReadRegisterClasses(); - return RegisterClasses; + /// getRegisterByName - If there is a register with the specific AsmName, + /// return it. + const CodeGenRegister *getRegisterByName(StringRef Name) const; + + const std::vector &getRegAltNameIndices() const { + if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); + return RegAltNameIndices; } - + const CodeGenRegisterClass &getRegisterClass(Record *R) const { - const std::vector &RC = getRegisterClasses(); - for (unsigned i = 0, e = RC.size(); i != e; ++i) - if (RC[i].TheDef == R) - return RC[i]; - assert(0 && "Didn't find the register class"); - abort(); + return *getRegBank().getRegClass(R); } - - /// getRegisterClassForRegister - Find the register class that contains the - /// specified physical register. If there register exists in multiple - /// register classes or is not in a register class, return null. - const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const { - const std::vector &RCs = getRegisterClasses(); - const CodeGenRegisterClass *FoundRC = 0; - for (unsigned i = 0, e = RCs.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RegisterClasses[i]; - for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { - if (R == RC.Elements[ei]) { - if (FoundRC) return 0; // In multiple RC's - FoundRC = &RC; - break; - } - } - } - return FoundRC; - } - - const std::vector &getLegalValueTypes() const { + + /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the + /// specified physical register. + std::vector getRegisterVTs(Record *R) const; + + ArrayRef getLegalValueTypes() const { if (LegalValueTypes.empty()) ReadLegalValueTypes(); return LegalValueTypes; } - + /// isLegalValueType - Return true if the specified value type is natively /// supported by the target (i.e. there are registers that directly hold it). - bool isLegalValueType(MVT::ValueType VT) const { - const std::vector &LegalVTs = getLegalValueTypes(); + bool isLegalValueType(MVT::SimpleValueType VT) const { + ArrayRef LegalVTs = getLegalValueTypes(); for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) if (LegalVTs[i] == VT) return true; - return false; + return false; } - /// getInstructions - Return all of the instructions defined for this target. - /// - const std::map &getInstructions() const { + CodeGenSchedModels &getSchedModels() const; + +private: + DenseMap &getInstructions() const { if (Instructions.empty()) ReadInstructions(); return Instructions; } +public: - CodeGenInstruction &getInstruction(const std::string &Name) const { - const std::map &Insts = getInstructions(); - assert(Insts.count(Name) && "Not an instruction!"); - return const_cast(Insts.find(Name)->second); + CodeGenInstruction &getInstruction(const Record *InstRec) const { + if (Instructions.empty()) ReadInstructions(); + DenseMap::iterator I = + Instructions.find(InstRec); + assert(I != Instructions.end() && "Not an instruction"); + return *I->second; } - typedef std::map::const_iterator inst_iterator; - inst_iterator inst_begin() const { return getInstructions().begin(); } - inst_iterator inst_end() const { return Instructions.end(); } - /// getInstructionsByEnumValue - Return all of the instructions defined by the /// target, ordered by their enum value. - void getInstructionsByEnumValue(std::vector - &NumberedInstructions); + const std::vector & + getInstructionsByEnumValue() const { + if (InstrsByEnum.empty()) ComputeInstrsByEnum(); + return InstrsByEnum; + } + typedef std::vector::const_iterator inst_iterator; + inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} + inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } - /// getPHIInstruction - Return the designated PHI instruction. - /// - const CodeGenInstruction &getPHIInstruction() const; /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? /// bool isLittleEndianEncoding() const; + + /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit + /// encodings, reverse the bit order of all instructions. + void reverseBitsForLittleEndianEncoding(); + + /// guessInstructionProperties - should we just guess unset instruction + /// properties? + bool guessInstructionProperties() const; + +private: + void ComputeInstrsByEnum() const; }; /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern /// tablegen class in TargetSelectionDAG.td class ComplexPattern { + MVT::SimpleValueType Ty; unsigned NumOperands; std::string SelectFunc; - std::vector MatchingNodes; + std::vector RootNodes; + unsigned Properties; // Node properties public: - ComplexPattern() : NumOperands(0) {}; + ComplexPattern() : NumOperands(0) {} ComplexPattern(Record *R); + MVT::SimpleValueType getValueType() const { return Ty; } unsigned getNumOperands() const { return NumOperands; } const std::string &getSelectFunc() const { return SelectFunc; } - const std::vector &getMatchingNodes() const { - return MatchingNodes; + const std::vector &getRootNodes() const { + return RootNodes; } + bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } }; } // End llvm namespace