X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=46fcdf5e96ffdcc48a4d17a94094ac94cbd64fdf;hb=0e496c884c86a50d4f024e6994f5b102118f9821;hp=15b35d5d5dbc8a7d875e3b9a7c84709b6f902666;hpb=485c00f7e8153e9d281c4f542593f503d022043c;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 15b35d5d5db..46fcdf5e96f 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -13,251 +13,314 @@ // //===----------------------------------------------------------------------===// -#include "CodeEmitterGen.h" #include "CodeGenTarget.h" -#include "Record.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" +#include +#include +#include using namespace llvm; -void CodeEmitterGen::emitInstrOpBits(std::ostream &o, - const std::vector &Vals, - std::map &OpOrder, - std::map &OpContinuous) -{ - for (unsigned f = 0, e = Vals.size(); f != e; ++f) { - if (Vals[f].getPrefix()) { - BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue(); - - // Scan through the field looking for bit initializers of the current - // variable... - for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) { - Init *I = FieldInitializer->getBit(i); - if (BitInit *BI = dynamic_cast(I)) { - DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n"); - } else if (UnsetInit *UI = dynamic_cast(I)) { - DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n"); - } else if (VarBitInit *VBI = dynamic_cast(I)) { - TypedInit *TI = VBI->getVariable(); - if (VarInit *VI = dynamic_cast(TI)) { - // If the bits of the field are laid out consecutively in the - // instruction, then instead of separately ORing in bits, just - // mask and shift the entire field for efficiency. - if (OpContinuous[VI->getName()]) { - // already taken care of in the loop above, thus there is no - // need to individually OR in the bits - - // for debugging, output the regular version anyway, commented - DEBUG(o << " // Value |= getValueBit(op" - << OpOrder[VI->getName()] << ", " << VBI->getBitNum() - << ")" << " << " << i << ";\n"); - } else { - o << " Value |= getValueBit(op" << OpOrder[VI->getName()] - << ", " << VBI->getBitNum() - << ")" << " << " << i << ";\n"; - } - } else if (FieldInit *FI = dynamic_cast(TI)) { - // FIXME: implement this! - std::cerr << "Error: FieldInit not implemented!\n"; - abort(); - } else { - std::cerr << "Error: unimplemented case in " - << "CodeEmitterGen::emitInstrOpBits()\n"; - abort(); - } - } +namespace { + +class CodeEmitterGen { + RecordKeeper &Records; +public: + CodeEmitterGen(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &o); +private: + int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); + std::string getInstructionCase(Record *R, CodeGenTarget &Target); + void AddCodeToMergeInOperand(Record *R, BitsInit *BI, + const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target); + +}; + +// If the VarBitInit at position 'bit' matches the specified variable then +// return the variable bit position. Otherwise return -1. +int CodeEmitterGen::getVariableBit(const std::string &VarName, + BitsInit *BI, int bit) { + if (VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + if (VarInit *VI = dyn_cast(VBI->getBitVar())) + if (VI->getName() == VarName) + return VBI->getBitNum(); + } else if (VarInit *VI = dyn_cast(BI->getBit(bit))) { + if (VI->getName() == VarName) + return 0; + } + + return -1; +} + +void CodeEmitterGen:: +AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target) { + CodeGenInstruction &CGI = Target.getInstruction(R); + + // Determine if VarName actually contributes to the Inst encoding. + int bit = BI->getNumBits()-1; + + // Scan for a bit that this contributed to. + for (; bit >= 0; ) { + if (getVariableBit(VarName, BI, bit) != -1) + break; + + --bit; + } + + // If we found no bits, ignore this value, otherwise emit the call to get the + // operand encoding. + if (bit < 0) return; + + // If the operand matches by name, reference according to that + // operand number. Non-matching operands are assumed to be in + // order. + unsigned OpIdx; + if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { + // Get the machine operand number for the indicated operand. + OpIdx = CGI.Operands[OpIdx].MIOperandNo; + assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && + "Explicitly used operand also marked as not emitted!"); + } else { + unsigned NumberOps = CGI.Operands.size(); + /// If this operand is not supposed to be emitted by the + /// generated emitter, skip it. + while (NumberedOp < NumberOps && + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) || + (!NamedOpIndices.empty() && NamedOpIndices.count( + CGI.Operands.getSubOperandNumber(NumberedOp).first)))) { + ++NumberedOp; + + if (NumberedOp >= CGI.Operands.back().MIOperandNo + + CGI.Operands.back().MINumOperands) { + errs() << "Too few operands in record " << R->getName() << + " (no match for variable " << VarName << "):\n"; + errs() << *R; + errs() << '\n'; + + return; } } + + OpIdx = NumberedOp++; + } + + std::pair SO = CGI.Operands.getSubOperandNumber(OpIdx); + std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName; + + // If the source operand has a custom encoder, use it. This will + // get the encoding for all of the suboperands. + if (!EncoderMethodName.empty()) { + // A custom encoder has all of the information for the + // sub-operands, if there are more than one, so only + // query the encoder once per source operand. + if (SO.second == 0) { + Case += " // op: " + VarName + "\n" + + " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); + Case += ", Fixups, STI"; + Case += ");\n"; + } + } else { + Case += " // op: " + VarName + "\n" + + " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; + Case += ", Fixups, STI"; + Case += ");\n"; + } + + for (; bit >= 0; ) { + int varBit = getVariableBit(VarName, BI, bit); + + // If this bit isn't from a variable, skip it. + if (varBit == -1) { + --bit; + continue; + } + + // Figure out the consecutive range of bits covered by this operand, in + // order to generate better encoding code. + int beginInstBit = bit; + int beginVarBit = varBit; + int N = 1; + for (--bit; bit >= 0;) { + varBit = getVariableBit(VarName, BI, bit); + if (varBit == -1 || varBit != (beginVarBit - N)) break; + ++N; + --bit; + } + + uint64_t opMask = ~(uint64_t)0 >> (64-N); + int opShift = beginVarBit - N + 1; + opMask <<= opShift; + opShift = beginInstBit - beginVarBit; + + if (opShift > 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " + + itostr(opShift) + ";\n"; + } else if (opShift < 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " + + itostr(-opShift) + ";\n"; + } else { + Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n"; + } } } -void CodeEmitterGen::run(std::ostream &o) { - CodeGenTarget Target; +std::string CodeEmitterGen::getInstructionCase(Record *R, + CodeGenTarget &Target) { + std::string Case; + + BitsInit *BI = R->getValueAsBitsInit("Inst"); + const std::vector &Vals = R->getValues(); + unsigned NumberedOp = 0; + + std::set NamedOpIndices; + // Collect the set of operand indices that might correspond to named + // operand, and skip these when assigning operands based on position. + if (Target.getInstructionSet()-> + getValueAsBit("noNamedPositionallyEncodedOperands")) { + CodeGenInstruction &CGI = Target.getInstruction(R); + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + unsigned OpIdx; + if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) + continue; + + NamedOpIndices.insert(OpIdx); + } + } + + // Loop over all of the fields in the instruction, determining which are the + // operands to the instruction. + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + // Ignore fixed fields in the record, we're looking for values like: + // bits<5> RST = { ?, ?, ?, ?, ? }; + if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete()) + continue; + + AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, + NamedOpIndices, Case, Target); + } + + std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); + if (!PostEmitter.empty()) { + Case += " Value = " + PostEmitter + "(MI, Value"; + Case += ", STI"; + Case += ");\n"; + } + + return Case; +} + +void CodeEmitterGen::run(raw_ostream &o) { + CodeGenTarget Target(Records); std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); - EmitSourceFileHeader("Machine Code Emitter", o); - std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; + // For little-endian instruction bit encodings, reverse the bit order + Target.reverseBitsForLittleEndianEncoding(); + + const std::vector &NumberedInstructions = + Target.getInstructionsByEnumValue(); // Emit function declaration - o << "unsigned " << Target.getName() << "CodeEmitter::" - << "getBinaryCodeForInstr(MachineInstr &MI) {\n" - << " unsigned Value = 0;\n" - << " DEBUG(std::cerr << MI);\n" - << " switch (MI.getOpcode()) {\n"; - - // Emit a case statement for each opcode - for (std::vector::iterator I = Insts.begin(), E = Insts.end(); - I != E; ++I) { - Record *R = *I; - if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue; - - o << " case " << Namespace << R->getName() << ": {\n" - << " DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n"; + o << "uint64_t " << Target.getName(); + o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + << " SmallVectorImpl &Fixups,\n" + << " const MCSubtargetInfo &STI) const {\n"; - BitsInit *BI = R->getValueAsBitsInit("Inst"); + // Emit instruction base values + o << " static const uint64_t InstBits[] = {\n"; + for (std::vector::const_iterator + IN = NumberedInstructions.begin(), + EN = NumberedInstructions.end(); + IN != EN; ++IN) { + const CodeGenInstruction *CGI = *IN; + Record *R = CGI->TheDef; - // For little-endian instruction bit encodings, reverse the bit order - if (Target.isLittleEndianEncoding()) { - unsigned numBits = BI->getNumBits(); - BitsInit *NewBI = new BitsInit(numBits); - for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { - unsigned bitSwapIdx = numBits - bit - 1; - Init *OrigBit = BI->getBit(bit); - Init *BitSwap = BI->getBit(bitSwapIdx); - NewBI->setBit(bit, BitSwap); - NewBI->setBit(bitSwapIdx, OrigBit); - } - if (numBits % 2) { - unsigned middle = (numBits + 1) / 2; - NewBI->setBit(middle, BI->getBit(middle)); - } - BI = NewBI; - - // Update the bits in reversed order so that emitInstrOpBits will get the - // correct endianness. - R->getValue("Inst")->setValue(NewBI); + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { + o << " UINT64_C(0),\n"; + continue; } - unsigned Value = 0; - const std::vector &Vals = R->getValues(); + BitsInit *BI = R->getValueAsBitsInit("Inst"); - DEBUG(o << " // prefilling: "); - // Start by filling in fixed values... + // Start by filling in fixed values. + uint64_t Value = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) { - Value |= B->getValue() << (e-i-1); - DEBUG(o << B->getValue()); - } else { - DEBUG(o << "0"); - } + if (BitInit *B = dyn_cast(BI->getBit(e-i-1))) + Value |= (uint64_t)B->getValue() << (e-i-1); } - DEBUG(o << "\n"); + o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n"; + } + o << " UINT64_C(0)\n };\n"; - DEBUG(o << " // " << *R->getValue("Inst") << "\n"); - o << " Value = " << Value << "U;\n\n"; + // Map to accumulate all the cases. + std::map > CaseMap; - // Loop over all of the fields in the instruction, determining which are the - // operands to the instruction. - unsigned op = 0; - std::map OpOrder; - std::map OpContinuous; - for (unsigned i = 0, e = Vals.size(); i != e; ++i) { - if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) { - // Is the operand continuous? If so, we can just mask and OR it in - // instead of doing it bit-by-bit, saving a lot in runtime cost. - BitsInit *InstInit = BI; - int beginBitInVar = -1, endBitInVar = -1; - int beginBitInInst = -1, endBitInInst = -1; - bool continuous = true; - - for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) { - if (VarBitInit *VBI = - dynamic_cast(InstInit->getBit(bit))) { - TypedInit *TI = VBI->getVariable(); - if (VarInit *VI = dynamic_cast(TI)) { - // only process the current variable - if (VI->getName() != Vals[i].getName()) - continue; - - if (beginBitInVar == -1) - beginBitInVar = VBI->getBitNum(); - - if (endBitInVar == -1) - endBitInVar = VBI->getBitNum(); - else { - if (endBitInVar == (int)VBI->getBitNum() + 1) - endBitInVar = VBI->getBitNum(); - else { - continuous = false; - break; - } - } - - if (beginBitInInst == -1) - beginBitInInst = bit; - if (endBitInInst == -1) - endBitInInst = bit; - else { - if (endBitInInst == bit + 1) - endBitInInst = bit; - else { - continuous = false; - break; - } - } - - // maintain same distance between bits in field and bits in - // instruction. if the relative distances stay the same - // throughout, - if (beginBitInVar - (int)VBI->getBitNum() != - beginBitInInst - bit) { - continuous = false; - break; - } - } - } - } - - // If we have found no bit in "Inst" which comes from this field, then - // this is not an operand!! - if (beginBitInInst != -1) { - o << " // op" << op << ": " << Vals[i].getName() << "\n" - << " int op" << op - <<" = getMachineOpValue(MI, MI.getOperand("<= 0 && "Negative shift amount in masking!"); - if (endBitInVar != 0) { - o << " op" << OpOrder[Vals[i].getName()] - << " >>= " << endBitInVar << ";\n"; - beginBitInVar -= endBitInVar; - endBitInVar = 0; - } - - // High mask - o << " op" << OpOrder[Vals[i].getName()] - << " &= (1<<" << beginBitInVar+1 << ") - 1;\n"; - - // Shift the value to the correct place (according to place in inst) - assert(endBitInInst >= 0 && "Negative shift amount!"); - if (endBitInInst != 0) - o << " op" << OpOrder[Vals[i].getName()] - << " <<= " << endBitInInst << ";\n"; - - // Just OR in the result - o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n"; - } - - // otherwise, will be taken care of in the loop below using this - // value: - OpContinuous[Vals[i].getName()] = continuous; - } - } - } + // Construct all cases statement for each opcode + for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); + IC != EC; ++IC) { + Record *R = *IC; + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) + continue; + const std::string &InstName = R->getValueAsString("Namespace") + "::" + + R->getName(); + std::string Case = getInstructionCase(R, Target); + + CaseMap[Case].push_back(InstName); + } + + // Emit initial function code + o << " const unsigned opcode = MI.getOpcode();\n" + << " uint64_t Value = InstBits[opcode];\n" + << " uint64_t op = 0;\n" + << " (void)op; // suppress warning\n" + << " switch (opcode) {\n"; - emitInstrOpBits(o, Vals, OpOrder, OpContinuous); + // Emit each case statement + std::map >::iterator IE, EE; + for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { + const std::string &Case = IE->first; + std::vector &InstList = IE->second; + for (int i = 0, N = InstList.size(); i < N; i++) { + if (i) o << "\n"; + o << " case " << InstList[i] << ":"; + } + o << " {\n"; + o << Case; o << " break;\n" << " }\n"; } // Default case: unhandled opcode o << " default:\n" - << " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n" - << " abort();\n" + << " std::string msg;\n" + << " raw_string_ostream Msg(msg);\n" + << " Msg << \"Not supported instr: \" << MI;\n" + << " report_fatal_error(Msg.str());\n" << " }\n" << " return Value;\n" << "}\n\n"; } + +} // End anonymous namespace + +namespace llvm { + +void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Machine Code Emitter", OS); + CodeEmitterGen(RK).run(OS); +} + +} // End llvm namespace