X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=11911b63b7bd5365d5eba2136d0ee456e579b78c;hb=875710a2fd6b3c4f814961582594bd5c1cdb493a;hp=e9f30bec3c089071c017e84180ac95a8a2c5ef1f;hpb=7004b9cf337c0ebdb778c157529def6ad425ba5b;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index e9f30bec3c0..11911b63b7b 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -13,213 +13,278 @@ // //===----------------------------------------------------------------------===// -#include "CodeEmitterGen.h" #include "CodeGenTarget.h" -#include "Record.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" +#include +#include +#include using namespace llvm; -void CodeEmitterGen::reverseBits(std::vector &Insts) { - for (std::vector::iterator I = Insts.begin(), E = Insts.end(); - I != E; ++I) { - Record *R = *I; - if (R->getName() == "PHI" || - R->getName() == "INLINEASM" || - R->getName() == "DBG_LABEL" || - R->getName() == "EH_LABEL" || - R->getName() == "GC_LABEL" || - R->getName() == "KILL" || - R->getName() == "EXTRACT_SUBREG" || - R->getName() == "INSERT_SUBREG" || - R->getName() == "IMPLICIT_DEF" || - R->getName() == "SUBREG_TO_REG" || - R->getName() == "COPY_TO_REGCLASS") continue; +namespace { - BitsInit *BI = R->getValueAsBitsInit("Inst"); +class CodeEmitterGen { + RecordKeeper &Records; +public: + CodeEmitterGen(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &o); +private: + int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); + std::string getInstructionCase(Record *R, CodeGenTarget &Target); + void AddCodeToMergeInOperand(Record *R, BitsInit *BI, + const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target); + +}; + +// If the VarBitInit at position 'bit' matches the specified variable then +// return the variable bit position. Otherwise return -1. +int CodeEmitterGen::getVariableBit(const std::string &VarName, + BitsInit *BI, int bit) { + if (VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + if (VarInit *VI = dyn_cast(VBI->getBitVar())) + if (VI->getName() == VarName) + return VBI->getBitNum(); + } else if (VarInit *VI = dyn_cast(BI->getBit(bit))) { + if (VI->getName() == VarName) + return 0; + } + + return -1; +} - unsigned numBits = BI->getNumBits(); - BitsInit *NewBI = new BitsInit(numBits); - for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { - unsigned bitSwapIdx = numBits - bit - 1; - Init *OrigBit = BI->getBit(bit); - Init *BitSwap = BI->getBit(bitSwapIdx); - NewBI->setBit(bit, BitSwap); - NewBI->setBit(bitSwapIdx, OrigBit); +void CodeEmitterGen:: +AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target) { + CodeGenInstruction &CGI = Target.getInstruction(R); + + // Determine if VarName actually contributes to the Inst encoding. + int bit = BI->getNumBits()-1; + + // Scan for a bit that this contributed to. + for (; bit >= 0; ) { + if (getVariableBit(VarName, BI, bit) != -1) + break; + + --bit; + } + + // If we found no bits, ignore this value, otherwise emit the call to get the + // operand encoding. + if (bit < 0) return; + + // If the operand matches by name, reference according to that + // operand number. Non-matching operands are assumed to be in + // order. + unsigned OpIdx; + if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { + // Get the machine operand number for the indicated operand. + OpIdx = CGI.Operands[OpIdx].MIOperandNo; + assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && + "Explicitly used operand also marked as not emitted!"); + } else { + unsigned NumberOps = CGI.Operands.size(); + /// If this operand is not supposed to be emitted by the + /// generated emitter, skip it. + while (NumberedOp < NumberOps && + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) || + (NamedOpIndices.size() && NamedOpIndices.count( + CGI.Operands.getSubOperandNumber(NumberedOp).first)))) { + ++NumberedOp; + + if (NumberedOp >= CGI.Operands.back().MIOperandNo + + CGI.Operands.back().MINumOperands) { + errs() << "Too few operands in record " << R->getName() << + " (no match for variable " << VarName << "):\n"; + errs() << *R; + errs() << '\n'; + + return; + } } - if (numBits % 2) { - unsigned middle = (numBits + 1) / 2; - NewBI->setBit(middle, BI->getBit(middle)); + + OpIdx = NumberedOp++; + } + + std::pair SO = CGI.Operands.getSubOperandNumber(OpIdx); + std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName; + + // If the source operand has a custom encoder, use it. This will + // get the encoding for all of the suboperands. + if (!EncoderMethodName.empty()) { + // A custom encoder has all of the information for the + // sub-operands, if there are more than one, so only + // query the encoder once per source operand. + if (SO.second == 0) { + Case += " // op: " + VarName + "\n" + + " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); + Case += ", Fixups, STI"; + Case += ");\n"; + } + } else { + Case += " // op: " + VarName + "\n" + + " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; + Case += ", Fixups, STI"; + Case += ");\n"; + } + + for (; bit >= 0; ) { + int varBit = getVariableBit(VarName, BI, bit); + + // If this bit isn't from a variable, skip it. + if (varBit == -1) { + --bit; + continue; } - // Update the bits in reversed order so that emitInstrOpBits will get the - // correct endianness. - R->getValue("Inst")->setValue(NewBI); + // Figure out the consecutive range of bits covered by this operand, in + // order to generate better encoding code. + int beginInstBit = bit; + int beginVarBit = varBit; + int N = 1; + for (--bit; bit >= 0;) { + varBit = getVariableBit(VarName, BI, bit); + if (varBit == -1 || varBit != (beginVarBit - N)) break; + ++N; + --bit; + } + + uint64_t opMask = ~(uint64_t)0 >> (64-N); + int opShift = beginVarBit - N + 1; + opMask <<= opShift; + opShift = beginInstBit - beginVarBit; + + if (opShift > 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " + + itostr(opShift) + ";\n"; + } else if (opShift < 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " + + itostr(-opShift) + ";\n"; + } else { + Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n"; + } } } -// If the VarBitInit at position 'bit' matches the specified variable then -// return the variable bit position. Otherwise return -1. -int CodeEmitterGen::getVariableBit(const Init *VarVal, - BitsInit *BI, int bit) { - if (VarBitInit *VBI = dynamic_cast(BI->getBit(bit))) { - TypedInit *TI = VBI->getVariable(); - if (TI == VarVal) return VBI->getBitNum(); - } +std::string CodeEmitterGen::getInstructionCase(Record *R, + CodeGenTarget &Target) { + std::string Case; - return -1; -} + BitsInit *BI = R->getValueAsBitsInit("Inst"); + const std::vector &Vals = R->getValues(); + unsigned NumberedOp = 0; + std::set NamedOpIndices; + // Collect the set of operand indices that might correspond to named + // operand, and skip these when assigning operands based on position. + if (Target.getInstructionSet()-> + getValueAsBit("noNamedPositionallyEncodedOperands")) { + CodeGenInstruction &CGI = Target.getInstruction(R); + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + unsigned OpIdx; + if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) + continue; + + NamedOpIndices.insert(OpIdx); + } + } + + // Loop over all of the fields in the instruction, determining which are the + // operands to the instruction. + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + // Ignore fixed fields in the record, we're looking for values like: + // bits<5> RST = { ?, ?, ?, ?, ? }; + if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete()) + continue; + + AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, + NamedOpIndices, Case, Target); + } + + std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); + if (!PostEmitter.empty()) { + Case += " Value = " + PostEmitter + "(MI, Value"; + Case += ", STI"; + Case += ");\n"; + } + + return Case; +} void CodeEmitterGen::run(raw_ostream &o) { - CodeGenTarget Target; + CodeGenTarget Target(Records); std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); - + // For little-endian instruction bit encodings, reverse the bit order - if (Target.isLittleEndianEncoding()) reverseBits(Insts); + Target.reverseBitsForLittleEndianEncoding(); - EmitSourceFileHeader("Machine Code Emitter", o); - std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; - - std::vector NumberedInstructions; - Target.getInstructionsByEnumValue(NumberedInstructions); + const std::vector &NumberedInstructions = + Target.getInstructionsByEnumValue(); // Emit function declaration - o << "unsigned " << Target.getName() << "CodeEmitter::" - << "getBinaryCodeForInstr(const MachineInstr &MI) {\n"; + o << "uint64_t " << Target.getName(); + o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + << " SmallVectorImpl &Fixups,\n" + << " const MCSubtargetInfo &STI) const {\n"; // Emit instruction base values - o << " static const unsigned InstBits[] = {\n"; - for (std::vector::iterator + o << " static const uint64_t InstBits[] = {\n"; + for (std::vector::const_iterator IN = NumberedInstructions.begin(), EN = NumberedInstructions.end(); IN != EN; ++IN) { const CodeGenInstruction *CGI = *IN; Record *R = CGI->TheDef; - - if (R->getName() == "PHI" || - R->getName() == "INLINEASM" || - R->getName() == "DBG_LABEL" || - R->getName() == "EH_LABEL" || - R->getName() == "GC_LABEL" || - R->getName() == "KILL" || - R->getName() == "EXTRACT_SUBREG" || - R->getName() == "INSERT_SUBREG" || - R->getName() == "IMPLICIT_DEF" || - R->getName() == "SUBREG_TO_REG" || - R->getName() == "COPY_TO_REGCLASS") { - o << " 0U,\n"; + + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { + o << " UINT64_C(0),\n"; continue; } - + BitsInit *BI = R->getValueAsBitsInit("Inst"); - // Start by filling in fixed values... - unsigned Value = 0; + // Start by filling in fixed values. + uint64_t Value = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) { - Value |= B->getValue() << (e-i-1); - } + if (BitInit *B = dyn_cast(BI->getBit(e-i-1))) + Value |= (uint64_t)B->getValue() << (e-i-1); } - o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n"; + o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n"; } - o << " 0U\n };\n"; - + o << " UINT64_C(0)\n };\n"; + // Map to accumulate all the cases. std::map > CaseMap; - + // Construct all cases statement for each opcode for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); IC != EC; ++IC) { Record *R = *IC; - const std::string &InstName = R->getName(); - std::string Case(""); - - if (InstName == "PHI" || - InstName == "INLINEASM" || - InstName == "DBG_LABEL"|| - InstName == "EH_LABEL"|| - InstName == "GC_LABEL"|| - InstName == "KILL"|| - InstName == "EXTRACT_SUBREG" || - InstName == "INSERT_SUBREG" || - InstName == "IMPLICIT_DEF" || - InstName == "SUBREG_TO_REG" || - InstName == "COPY_TO_REGCLASS") continue; - - BitsInit *BI = R->getValueAsBitsInit("Inst"); - const std::vector &Vals = R->getValues(); - CodeGenInstruction &CGI = Target.getInstruction(InstName); - - // Loop over all of the fields in the instruction, determining which are the - // operands to the instruction. - unsigned op = 0; - for (unsigned i = 0, e = Vals.size(); i != e; ++i) { - if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) { - // Is the operand continuous? If so, we can just mask and OR it in - // instead of doing it bit-by-bit, saving a lot in runtime cost. - const Init *VarVal = Vals[i].getValue(); - bool gotOp = false; - - for (int bit = BI->getNumBits()-1; bit >= 0; ) { - int varBit = getVariableBit(VarVal, BI, bit); - - if (varBit == -1) { - --bit; - } else { - int beginInstBit = bit; - int beginVarBit = varBit; - int N = 1; - - for (--bit; bit >= 0;) { - varBit = getVariableBit(VarVal, BI, bit); - if (varBit == -1 || varBit != (beginVarBit - N)) break; - ++N; - --bit; - } - - if (!gotOp) { - /// If this operand is not supposed to be emitted by the generated - /// emitter, skip it. - while (CGI.isFlatOperandNotEmitted(op)) - ++op; - - Case += " // op: " + Vals[i].getName() + "\n" - + " op = getMachineOpValue(MI, MI.getOperand(" - + utostr(op++) + "));\n"; - gotOp = true; - } - - unsigned opMask = ~0U >> (32-N); - int opShift = beginVarBit - N + 1; - opMask <<= opShift; - opShift = beginInstBit - beginVarBit; - - if (opShift > 0) { - Case += " Value |= (op & " + utostr(opMask) + "U) << " - + itostr(opShift) + ";\n"; - } else if (opShift < 0) { - Case += " Value |= (op & " + utostr(opMask) + "U) >> " - + itostr(-opShift) + ";\n"; - } else { - Case += " Value |= op & " + utostr(opMask) + "U;\n"; - } - } - } - } - } + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) + continue; + const std::string &InstName = R->getValueAsString("Namespace") + "::" + + R->getName(); + std::string Case = getInstructionCase(R, Target); - std::vector &InstList = CaseMap[Case]; - InstList.push_back(InstName); + CaseMap[Case].push_back(InstName); } - // Emit initial function code o << " const unsigned opcode = MI.getOpcode();\n" - << " unsigned Value = InstBits[opcode];\n" - << " unsigned op = 0;\n" - << " op = op; // suppress warning\n" + << " uint64_t Value = InstBits[opcode];\n" + << " uint64_t op = 0;\n" + << " (void)op; // suppress warning\n" << " switch (opcode) {\n"; // Emit each case statement @@ -230,7 +295,7 @@ void CodeEmitterGen::run(raw_ostream &o) { for (int i = 0, N = InstList.size(); i < N; i++) { if (i) o << "\n"; - o << " case " << Namespace << InstList[i] << ":"; + o << " case " << InstList[i] << ":"; } o << " {\n"; o << Case; @@ -243,8 +308,19 @@ void CodeEmitterGen::run(raw_ostream &o) { << " std::string msg;\n" << " raw_string_ostream Msg(msg);\n" << " Msg << \"Not supported instr: \" << MI;\n" - << " llvm_report_error(Msg.str());\n" + << " report_fatal_error(Msg.str());\n" << " }\n" << " return Value;\n" << "}\n\n"; } + +} // End anonymous namespace + +namespace llvm { + +void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Machine Code Emitter", OS); + CodeEmitterGen(RK).run(OS); +} + +} // End llvm namespace