X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=11911b63b7bd5365d5eba2136d0ee456e579b78c;hb=875710a2fd6b3c4f814961582594bd5c1cdb493a;hp=e60aec9568ff9b950870593f467f1522a1159a75;hpb=6cfc806a6b82b60a3e923b6b89f2b4da62cdb50b;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index e60aec9568f..11911b63b7b 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -14,24 +14,16 @@ //===----------------------------------------------------------------------===// #include "CodeGenTarget.h" -#include "llvm/TableGen/Record.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" #include #include #include using namespace llvm; -// FIXME: Somewhat hackish to use a command line option for this. There should -// be a CodeEmitter class in the Target.td that controls this sort of thing -// instead. -static cl::opt -MCEmitter("mc-emitter", - cl::desc("Generate CodeEmitter for use with the MC library."), - cl::init(false)); - namespace { class CodeEmitterGen { @@ -41,52 +33,16 @@ public: void run(raw_ostream &o); private: - void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace); - void emitGetValueBit(raw_ostream &o, const std::string &Namespace); - void reverseBits(std::vector &Insts); int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); std::string getInstructionCase(Record *R, CodeGenTarget &Target); void AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, unsigned &NumberedOp, + std::set &NamedOpIndices, std::string &Case, CodeGenTarget &Target); }; -void CodeEmitterGen::reverseBits(std::vector &Insts) { - for (std::vector::iterator I = Insts.begin(), E = Insts.end(); - I != E; ++I) { - Record *R = *I; - if (R->getValueAsString("Namespace") == "TargetOpcode" || - R->getValueAsBit("isPseudo")) - continue; - - BitsInit *BI = R->getValueAsBitsInit("Inst"); - - unsigned numBits = BI->getNumBits(); - - SmallVector NewBits(numBits); - - for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { - unsigned bitSwapIdx = numBits - bit - 1; - Init *OrigBit = BI->getBit(bit); - Init *BitSwap = BI->getBit(bitSwapIdx); - NewBits[bit] = BitSwap; - NewBits[bitSwapIdx] = OrigBit; - } - if (numBits % 2) { - unsigned middle = (numBits + 1) / 2; - NewBits[middle] = BI->getBit(middle); - } - - BitsInit *NewBI = BitsInit::get(NewBits); - - // Update the bits in reversed order so that emitInstrOpBits will get the - // correct endianness. - R->getValue("Inst")->setValue(NewBI); - } -} - // If the VarBitInit at position 'bit' matches the specified variable then // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, @@ -106,6 +62,7 @@ int CodeEmitterGen::getVariableBit(const std::string &VarName, void CodeEmitterGen:: AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, unsigned &NumberedOp, + std::set &NamedOpIndices, std::string &Case, CodeGenTarget &Target) { CodeGenInstruction &CGI = Target.getInstruction(R); @@ -134,10 +91,26 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && "Explicitly used operand also marked as not emitted!"); } else { + unsigned NumberOps = CGI.Operands.size(); /// If this operand is not supposed to be emitted by the /// generated emitter, skip it. - while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp)) + while (NumberedOp < NumberOps && + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) || + (NamedOpIndices.size() && NamedOpIndices.count( + CGI.Operands.getSubOperandNumber(NumberedOp).first)))) { ++NumberedOp; + + if (NumberedOp >= CGI.Operands.back().MIOperandNo + + CGI.Operands.back().MINumOperands) { + errs() << "Too few operands in record " << R->getName() << + " (no match for variable " << VarName << "):\n"; + errs() << *R; + errs() << '\n'; + + return; + } + } + OpIdx = NumberedOp++; } @@ -153,15 +126,13 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, if (SO.second == 0) { Case += " // op: " + VarName + "\n" + " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); - if (MCEmitter) - Case += ", Fixups"; + Case += ", Fixups, STI"; Case += ");\n"; } } else { Case += " // op: " + VarName + "\n" + " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; - if (MCEmitter) - Case += ", Fixups"; + Case += ", Fixups, STI"; Case += ");\n"; } @@ -212,6 +183,21 @@ std::string CodeEmitterGen::getInstructionCase(Record *R, const std::vector &Vals = R->getValues(); unsigned NumberedOp = 0; + std::set NamedOpIndices; + // Collect the set of operand indices that might correspond to named + // operand, and skip these when assigning operands based on position. + if (Target.getInstructionSet()-> + getValueAsBit("noNamedPositionallyEncodedOperands")) { + CodeGenInstruction &CGI = Target.getInstruction(R); + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + unsigned OpIdx; + if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) + continue; + + NamedOpIndices.insert(OpIdx); + } + } + // Loop over all of the fields in the instruction, determining which are the // operands to the instruction. for (unsigned i = 0, e = Vals.size(); i != e; ++i) { @@ -220,12 +206,16 @@ std::string CodeEmitterGen::getInstructionCase(Record *R, if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete()) continue; - AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target); + AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, + NamedOpIndices, Case, Target); } std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); - if (!PostEmitter.empty()) - Case += " Value = " + PostEmitter + "(MI, Value);\n"; + if (!PostEmitter.empty()) { + Case += " Value = " + PostEmitter + "(MI, Value"; + Case += ", STI"; + Case += ");\n"; + } return Case; } @@ -235,19 +225,16 @@ void CodeEmitterGen::run(raw_ostream &o) { std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); // For little-endian instruction bit encodings, reverse the bit order - if (Target.isLittleEndianEncoding()) reverseBits(Insts); - + Target.reverseBitsForLittleEndianEncoding(); const std::vector &NumberedInstructions = Target.getInstructionsByEnumValue(); // Emit function declaration o << "uint64_t " << Target.getName(); - if (MCEmitter) - o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" - << " SmallVectorImpl &Fixups) const {\n"; - else - o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n"; + o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + << " SmallVectorImpl &Fixups,\n" + << " const MCSubtargetInfo &STI) const {\n"; // Emit instruction base values o << " static const uint64_t InstBits[] = {\n";