X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=11911b63b7bd5365d5eba2136d0ee456e579b78c;hb=875710a2fd6b3c4f814961582594bd5c1cdb493a;hp=a4ff4eec1e47d9c5ecc5b6ca359a15af8661b60f;hpb=4faa861f19b73cfd8e537e2af5379d6ba53c82d0;p=oota-llvm.git

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index a4ff4eec1e4..11911b63b7b 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -24,14 +24,6 @@
 #include <vector>
 using namespace llvm;
 
-// FIXME: Somewhat hackish to use a command line option for this. There should
-// be a CodeEmitter class in the Target.td that controls this sort of thing
-// instead.
-static cl::opt<bool>
-MCEmitter("mc-emitter",
-          cl::desc("Generate CodeEmitter for use with the MC library."),
-          cl::init(false));
-
 namespace {
 
 class CodeEmitterGen {
@@ -41,13 +33,12 @@ public:
 
   void run(raw_ostream &o);
 private:
-  void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
-  void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
   int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
   std::string getInstructionCase(Record *R, CodeGenTarget &Target);
   void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
                                const std::string &VarName,
                                unsigned &NumberedOp,
+                               std::set<unsigned> &NamedOpIndices,
                                std::string &Case, CodeGenTarget &Target);
 
 };
@@ -71,6 +62,7 @@ int CodeEmitterGen::getVariableBit(const std::string &VarName,
 void CodeEmitterGen::
 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
                         unsigned &NumberedOp,
+                        std::set<unsigned> &NamedOpIndices,
                         std::string &Case, CodeGenTarget &Target) {
   CodeGenInstruction &CGI = Target.getInstruction(R);
 
@@ -103,9 +95,22 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
     /// If this operand is not supposed to be emitted by the
     /// generated emitter, skip it.
     while (NumberedOp < NumberOps &&
-           CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
+           (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
+              (NamedOpIndices.size() && NamedOpIndices.count(
+                CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
       ++NumberedOp;
 
+      if (NumberedOp >= CGI.Operands.back().MIOperandNo +
+                        CGI.Operands.back().MINumOperands) {
+        errs() << "Too few operands in record " << R->getName() <<
+                  " (no match for variable " << VarName << "):\n";
+        errs() << *R;
+        errs() << '\n';
+
+        return;
+      }
+    }
+
     OpIdx = NumberedOp++;
   }
   
@@ -121,15 +126,13 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
     if (SO.second == 0) {
       Case += "      // op: " + VarName + "\n" +
               "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
-      if (MCEmitter)
-        Case += ", Fixups, STI";
+      Case += ", Fixups, STI";
       Case += ");\n";
     }
   } else {
     Case += "      // op: " + VarName + "\n" +
       "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
-    if (MCEmitter)
-      Case += ", Fixups, STI";
+    Case += ", Fixups, STI";
     Case += ");\n";
   }
   
@@ -180,6 +183,21 @@ std::string CodeEmitterGen::getInstructionCase(Record *R,
   const std::vector<RecordVal> &Vals = R->getValues();
   unsigned NumberedOp = 0;
 
+  std::set<unsigned> NamedOpIndices;
+  // Collect the set of operand indices that might correspond to named
+  // operand, and skip these when assigning operands based on position.
+  if (Target.getInstructionSet()->
+       getValueAsBit("noNamedPositionallyEncodedOperands")) {
+    CodeGenInstruction &CGI = Target.getInstruction(R);
+    for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
+      unsigned OpIdx;
+      if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
+        continue;
+
+      NamedOpIndices.insert(OpIdx);
+    }
+  }
+
   // Loop over all of the fields in the instruction, determining which are the
   // operands to the instruction.
   for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
@@ -188,14 +206,14 @@ std::string CodeEmitterGen::getInstructionCase(Record *R,
     if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
       continue;
     
-    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
+    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
+                            NamedOpIndices, Case, Target);
   }
   
   std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
   if (!PostEmitter.empty()) {
     Case += "      Value = " + PostEmitter + "(MI, Value";
-    if (MCEmitter)
-      Case += ", STI";
+    Case += ", STI";
     Case += ");\n";
   }
   
@@ -214,12 +232,9 @@ void CodeEmitterGen::run(raw_ostream &o) {
 
   // Emit function declaration
   o << "uint64_t " << Target.getName();
-  if (MCEmitter)
-    o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
-      << "    SmallVectorImpl<MCFixup> &Fixups,\n"
-      << "    const MCSubtargetInfo &STI) const {\n";
-  else
-    o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
+  o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
+    << "    SmallVectorImpl<MCFixup> &Fixups,\n"
+    << "    const MCSubtargetInfo &STI) const {\n";
 
   // Emit instruction base values
   o << "  static const uint64_t InstBits[] = {\n";