X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=a7fc7f3c3ea688ba3331d4f078d47a9b67cabc8a;hb=abfd63051d58992d37729a960d319a1eeeec32ae;hp=f9686fd9b5ad3f54e0fe763e38955743d5057558;hpb=eef965f04bab483a7d2fd46a7d51559197eda5cf;p=oota-llvm.git diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index f9686fd9b5a..a7fc7f3c3ea 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -12,16 +12,57 @@ // //===----------------------------------------------------------------------===// -#include "AsmWriterEmitter.h" #include "AsmWriterInst.h" #include "CodeGenTarget.h" -#include "Record.h" -#include "StringToOffsetTable.h" +#include "SequenceToOffsetTable.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" +#include "llvm/TableGen/Error.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" #include +#include +#include +#include using namespace llvm; +#define DEBUG_TYPE "asm-writer-emitter" + +namespace { +class AsmWriterEmitter { + RecordKeeper &Records; + CodeGenTarget Target; + std::map CGIAWIMap; + const std::vector *NumberedInstructions; + std::vector Instructions; + std::vector PrintMethods; +public: + AsmWriterEmitter(RecordKeeper &R); + + void run(raw_ostream &o); + +private: + void EmitPrintInstruction(raw_ostream &o); + void EmitGetRegisterName(raw_ostream &o); + void EmitPrintAliasInstruction(raw_ostream &O); + + AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { + assert(ID < NumberedInstructions->size()); + std::map::const_iterator I = + CGIAWIMap.find(NumberedInstructions->at(ID)); + assert(I != CGIAWIMap.end() && "Didn't find inst!"); + return I->second; + } + void FindUniqueOperandCommands(std::vector &UOC, + std::vector &InstIdxs, + std::vector &InstOpsUsed) const; +}; +} // end anonymous namespace + static void PrintCases(std::vector > &OpsToPrint, raw_ostream &O) { O << " case " << OpsToPrint.back().first << ": "; @@ -68,9 +109,9 @@ static void EmitInstructions(std::vector &Insts, O << " case " << FirstInst.CGI->Namespace << "::" << FirstInst.CGI->TheDef->getName() << ":\n"; - for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) - O << " case " << SimilarInsts[i].CGI->Namespace << "::" - << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; + for (const AsmWriterInst &AWI : SimilarInsts) + O << " case " << AWI.CGI->Namespace << "::" + << AWI.CGI->TheDef->getName() << ":\n"; for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { if (i != DifferingOperand) { // If the operand is the same for all instructions, just print it. @@ -84,8 +125,7 @@ static void EmitInstructions(std::vector &Insts, FirstInst.CGI->TheDef->getName(), FirstInst.Operands[i])); - for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { - AsmWriterInst &AWI = SimilarInsts[si]; + for (const AsmWriterInst &AWI : SimilarInsts) { OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ AWI.CGI->TheDef->getName(), AWI.Operands[i])); @@ -104,7 +144,7 @@ void AsmWriterEmitter:: FindUniqueOperandCommands(std::vector &UniqueOperandCommands, std::vector &InstIdxs, std::vector &InstOpsUsed) const { - InstIdxs.assign(NumberedInstructions.size(), ~0U); + InstIdxs.assign(NumberedInstructions->size(), ~0U); // This vector parallels UniqueOperandCommands, keeping track of which // instructions each case are used for. It is a comma separated string of @@ -113,15 +153,15 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, InstrsForCase.resize(UniqueOperandCommands.size()); InstOpsUsed.assign(UniqueOperandCommands.size(), 0); - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { const AsmWriterInst *Inst = getAsmWriterInstByID(i); - if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc. + if (!Inst) + continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc. - std::string Command; if (Inst->Operands.empty()) continue; // Instruction already done. - Command = " " + Inst->Operands[0].getCode() + "\n"; + std::string Command = " " + Inst->Operands[0].getCode() + "\n"; // Check to see if we already have 'Command' in UniqueOperandCommands. // If not, add it. @@ -136,7 +176,7 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, } if (!FoundIt) { InstIdxs[i] = UniqueOperandCommands.size(); - UniqueOperandCommands.push_back(Command); + UniqueOperandCommands.push_back(std::move(Command)); InstrsForCase.push_back(Inst->CGI->TheDef->getName()); // This command matches one operand so far. @@ -166,9 +206,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, // Otherwise, scan to see if all of the other instructions in this command // set share the operand. bool AllSame = true; - // Keep track of the maximum, number of operands or any - // instruction we see in the group. - size_t MaxSize = FirstInst->Operands.size(); for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); NIT != InstIdxs.end(); @@ -178,10 +215,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, const AsmWriterInst *OtherInst = getAsmWriterInstByID(NIT-InstIdxs.begin()); - if (OtherInst && - OtherInst->Operands.size() > FirstInst->Operands.size()) - MaxSize = std::max(MaxSize, OtherInst->Operands.size()); - if (!OtherInst || OtherInst->Operands.size() == Op || OtherInst->Operands[Op] != FirstInst->Operands[Op]) { AllSame = false; @@ -238,65 +271,60 @@ static void UnescapeString(std::string &Str) { } /// EmitPrintInstruction - Generate the code for the "printInstruction" method -/// implementation. +/// implementation. Destroys all instances of AsmWriterInst information, by +/// clearing the Instructions vector. void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); - const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr"; + unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); O << "/// printInstruction - This method is automatically generated by tablegen\n" "/// from the instruction set description.\n" "void " << Target.getName() << ClassName - << "::printInstruction(const " << MachineInstrClassName - << " *MI, raw_ostream &O) {\n"; - - std::vector Instructions; - - for (CodeGenTarget::inst_iterator I = Target.inst_begin(), - E = Target.inst_end(); I != E; ++I) - if (!(*I)->AsmString.empty() && - (*I)->TheDef->getName() != "PHI") - Instructions.push_back( - AsmWriterInst(**I, - AsmWriter->getValueAsInt("Variant"), - AsmWriter->getValueAsInt("FirstOperandColumn"), - AsmWriter->getValueAsInt("OperandSpacing"))); - - // Get the instruction numbering. - NumberedInstructions = Target.getInstructionsByEnumValue(); - - // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not - // all machine instructions are necessarily being printed, so there may be - // target instructions not in this map. - for (unsigned i = 0, e = Instructions.size(); i != e; ++i) - CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); + << "::printInstruction(const MCInst *MI, " + << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") + << "raw_ostream &O) {\n"; // Build an aggregate string, and build a table of offsets into it. - StringToOffsetTable StringTable; + SequenceToOffsetTable StringTable; /// OpcodeInfo - This encodes the index of the string to use for the first /// chunk of the output as well as indices used for operand printing. - std::vector OpcodeInfo; + std::vector OpcodeInfo; + + // Add all strings to the string table upfront so it can generate an optimized + // representation. + for (const CodeGenInstruction *Inst : *NumberedInstructions) { + AsmWriterInst *AWI = CGIAWIMap[Inst]; + if (AWI && + AWI->Operands[0].OperandType == + AsmWriterOperand::isLiteralTextOperand && + !AWI->Operands[0].Str.empty()) { + std::string Str = AWI->Operands[0].Str; + UnescapeString(Str); + StringTable.add(Str); + } + } + + StringTable.layout(); unsigned MaxStringIdx = 0; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; + for (const CodeGenInstruction *Inst : *NumberedInstructions) { + AsmWriterInst *AWI = CGIAWIMap[Inst]; unsigned Idx; - if (AWI == 0) { + if (!AWI) { // Something not handled by the asmwriter printer. Idx = ~0U; } else if (AWI->Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand || AWI->Operands[0].Str.empty()) { // Something handled by the asmwriter printer, but with no leading string. - Idx = StringTable.GetOrAddStringOffset(""); + Idx = StringTable.get(""); } else { std::string Str = AWI->Operands[0].Str; UnescapeString(Str); - Idx = StringTable.GetOrAddStringOffset(Str); + Idx = StringTable.get(Str); MaxStringIdx = std::max(MaxStringIdx, Idx); // Nuke the string from the operand list. It is now handled! @@ -312,9 +340,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // To reduce code size, we compactify common instructions into a few bits // in the opcode-indexed table. - unsigned BitsLeft = 32-AsmStrBits; + unsigned BitsLeft = 64-AsmStrBits; - std::vector > TableDrivenOperandPrinters; + std::vector> TableDrivenOperandPrinters; while (1) { std::vector UniqueOperandCommands; @@ -338,13 +366,14 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Otherwise, we can include this in the initial lookup table. Add it in. - BitsLeft -= NumBits; for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) - if (InstIdxs[i] != ~0U) - OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits); + if (InstIdxs[i] != ~0U) { + OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); + } + BitsLeft -= NumBits; // Remove the info about this operand. - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) if (!Inst->Operands.empty()) { unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; @@ -356,34 +385,57 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Remember the handlers for this set of operands. - TableDrivenOperandPrinters.push_back(UniqueOperandCommands); + TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); } - - - O<<" static const unsigned OpInfo[] = {\n"; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - O << " " << OpcodeInfo[i] << "U,\t// " - << NumberedInstructions[i]->TheDef->getName() << "\n"; - } - // Add a dummy entry so the array init doesn't end with a comma. - O << " 0U\n"; + // Emit the string table itself. + O << " static const char AsmStrs[] = {\n"; + StringTable.emit(O, printChar); O << " };\n\n"; - // Emit the string itself. - O << " const char *AsmStrs = \n"; - StringTable.EmitString(O); - O << ";\n\n"; + // Emit the lookup tables in pieces to minimize wasted bytes. + unsigned BytesNeeded = ((64 - BitsLeft) + 7) / 8; + unsigned Table = 0, Shift = 0; + SmallString<128> BitsString; + raw_svector_ostream BitsOS(BitsString); + // If the total bits is more than 32-bits we need to use a 64-bit type. + BitsOS << " uint" << ((BitsLeft < 32) ? 64 : 32) << "_t Bits = 0;\n"; + while (BytesNeeded != 0) { + // Figure out how big this table section needs to be, but no bigger than 4. + unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4); + BytesNeeded -= TableSize; + TableSize *= 8; // Convert to bits; + uint64_t Mask = (1ULL << TableSize) - 1; + O << " static const uint" << TableSize << "_t OpInfo" << Table + << "[] = {\n"; + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { + O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// " + << NumberedInstructions->at(i)->TheDef->getName() << "\n"; + } + O << " };\n\n"; + // Emit string to combine the individual table lookups. + BitsOS << " Bits |= "; + // If the total bits is more than 32-bits we need to use a 64-bit type. + if (BitsLeft < 32) + BitsOS << "(uint64_t)"; + BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; + // Prepare the shift for the next iteration and increment the table count. + Shift += TableSize; + ++Table; + } + // Emit the initial tab character. O << " O << \"\\t\";\n\n"; - O << " // Emit the opcode for the instruction.\n" - << " unsigned Bits = OpInfo[MI->getOpcode()];\n" - << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" + O << " // Emit the opcode for the instruction.\n"; + O << BitsString; + + // Emit the starting string. + O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; // Output the table driven operand information. - BitsLeft = 32-AsmStrBits; + BitsLeft = 64-AsmStrBits; for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { std::vector &Commands = TableDrivenOperandPrinters[i]; @@ -393,14 +445,13 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { assert(NumBits <= BitsLeft && "consistency error"); // Emit code to extract this field from Bits. - BitsLeft -= NumBits; - O << "\n // Fragment " << i << " encoded into " << NumBits << " bits for " << Commands.size() << " unique commands.\n"; if (Commands.size() == 2) { // Emit two possibilitys with if/else. - O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " + O << " if ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" << Commands[1] << " } else {\n" @@ -410,29 +461,28 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // Emit a single possibility. O << Commands[0] << "\n\n"; } else { - O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " + O << " switch ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" - << " default: // unreachable.\n"; + << " default: llvm_unreachable(\"Invalid command number.\");\n"; // Print out all the cases. - for (unsigned i = 0, e = Commands.size(); i != e; ++i) { - O << " case " << i << ":\n"; - O << Commands[i]; + for (unsigned j = 0, e = Commands.size(); j != e; ++j) { + O << " case " << j << ":\n"; + O << Commands[j]; O << " break;\n"; } O << " }\n\n"; } + BitsLeft -= NumBits; } // Okay, delete instructions with no operand info left. - for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { - // Entire instruction has been emitted? - AsmWriterInst &Inst = Instructions[i]; - if (Inst.Operands.empty()) { - Instructions.erase(Instructions.begin()+i); - --i; --e; - } - } + auto I = std::remove_if(Instructions.begin(), Instructions.end(), + [](AsmWriterInst &Inst) { + return Inst.Operands.empty(); + }); + Instructions.erase(I, Instructions.end()); // Because this is a vector, we want to emit from the end. Reverse all of the @@ -440,9 +490,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { std::reverse(Instructions.begin(), Instructions.end()); - // Now that we've emitted all of the operand info that fit into 32 bits, emit + // Now that we've emitted all of the operand info that fit into 64 bits, emit // information for those instructions that are left. This is a less dense - // encoding, but we expect the main 32-bit table to handle the majority of + // encoding, but we expect the main 64-bit table to handle the majority of // instructions. if (!Instructions.empty()) { // Find the opcode # of inline asm. @@ -457,178 +507,176 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { O << "}\n"; } +static const char *getMinimalTypeForRange(uint64_t Range) { + assert(Range < 0xFFFFFFFFULL && "Enum too large"); + if (Range > 0xFFFF) + return "uint32_t"; + if (Range > 0xFF) + return "uint16_t"; + return "uint8_t"; +} -void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { - CodeGenTarget Target(Records); - Record *AsmWriter = Target.getAsmWriter(); - std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - const std::vector &Registers = Target.getRegisters(); - - StringToOffsetTable StringTable; - O << - "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" - "/// from the register set description. This returns the assembler name\n" - "/// for the specified register.\n" - "const char *" << Target.getName() << ClassName - << "::getRegisterName(unsigned RegNo) {\n" - << " assert(RegNo && RegNo < " << (Registers.size()+1) - << " && \"Invalid register number!\");\n" - << "\n" - << " static const unsigned RegAsmOffset[] = {"; - for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - const CodeGenRegister &Reg = Registers[i]; - - std::string AsmName = Reg.TheDef->getValueAsString("AsmName"); - if (AsmName.empty()) - AsmName = Reg.getName(); +static void +emitRegisterNameString(raw_ostream &O, StringRef AltName, + const std::deque &Registers) { + SequenceToOffsetTable StringTable; + SmallVector AsmNames(Registers.size()); + unsigned i = 0; + for (const auto &Reg : Registers) { + std::string &AsmName = AsmNames[i++]; + + // "NoRegAltName" is special. We don't need to do a lookup for that, + // as it's just a reference to the default register name. + if (AltName == "" || AltName == "NoRegAltName") { + AsmName = Reg.TheDef->getValueAsString("AsmName"); + if (AsmName.empty()) + AsmName = Reg.getName(); + } else { + // Make sure the register has an alternate name for this index. + std::vector AltNameList = + Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); + unsigned Idx = 0, e; + for (e = AltNameList.size(); + Idx < e && (AltNameList[Idx]->getName() != AltName); + ++Idx) + ; + // If the register has an alternate name for this index, use it. + // Otherwise, leave it empty as an error flag. + if (Idx < e) { + std::vector AltNames = + Reg.TheDef->getValueAsListOfStrings("AltNames"); + if (AltNames.size() <= Idx) + PrintFatalError(Reg.TheDef->getLoc(), + "Register definition missing alt name for '" + + AltName + "'."); + AsmName = AltNames[Idx]; + } + } + StringTable.add(AsmName); + } + StringTable.layout(); + O << " static const char AsmStrs" << AltName << "[] = {\n"; + StringTable.emit(O, printChar); + O << " };\n\n"; + O << " static const " << getMinimalTypeForRange(StringTable.size()-1) + << " RegAsmOffset" << AltName << "[] = {"; + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { if ((i % 14) == 0) O << "\n "; - - O << StringTable.GetOrAddStringOffset(AsmName) << ", "; + O << StringTable.get(AsmNames[i]) << ", "; } - O << "0\n" - << " };\n" + O << "\n };\n" << "\n"; - - O << " const char *AsmStrs =\n"; - StringTable.EmitString(O); - O << ";\n"; - - O << " return AsmStrs+RegAsmOffset[RegNo-1];\n" - << "}\n"; } -void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) { - CodeGenTarget Target(Records); +void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); + const auto &Registers = Target.getRegBank().getRegisters(); + std::vector AltNameIndices = Target.getRegAltNameIndices(); + bool hasAltNames = AltNameIndices.size() > 1; + std::string Namespace = + Registers.front().TheDef->getValueAsString("Namespace"); - const std::vector &NumberedInstructions = - Target.getInstructionsByEnumValue(); - - StringToOffsetTable StringTable; O << -"\n\n#ifdef GET_INSTRUCTION_NAME\n" -"#undef GET_INSTRUCTION_NAME\n\n" -"/// getInstructionName: This method is automatically generated by tblgen\n" -"/// from the instruction set description. This returns the enum name of the\n" -"/// specified instruction.\n" - "const char *" << Target.getName() << ClassName - << "::getInstructionName(unsigned Opcode) {\n" - << " assert(Opcode < " << NumberedInstructions.size() - << " && \"Invalid instruction number!\");\n" - << "\n" - << " static const unsigned InstAsmOffset[] = {"; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - const CodeGenInstruction &Inst = *NumberedInstructions[i]; - - std::string AsmName = Inst.TheDef->getName(); - if ((i % 14) == 0) - O << "\n "; + "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" + "/// from the register set description. This returns the assembler name\n" + "/// for the specified register.\n" + "const char *" << Target.getName() << ClassName << "::"; + if (hasAltNames) + O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; + else + O << "getRegisterName(unsigned RegNo) {\n"; + O << " assert(RegNo && RegNo < " << (Registers.size()+1) + << " && \"Invalid register number!\");\n" + << "\n"; - O << StringTable.GetOrAddStringOffset(AsmName) << ", "; + if (hasAltNames) { + for (const Record *R : AltNameIndices) + emitRegisterNameString(O, R->getName(), Registers); + } else + emitRegisterNameString(O, "", Registers); + + if (hasAltNames) { + O << " switch(AltIdx) {\n" + << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; + for (const Record *R : AltNameIndices) { + std::string AltName(R->getName()); + std::string Prefix = !Namespace.empty() ? Namespace + "::" : ""; + O << " case " << Prefix << AltName << ":\n" + << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" + << AltName << "[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n" + << " return AsmStrs" << AltName << "+RegAsmOffset" + << AltName << "[RegNo-1];\n"; + } + O << " }\n"; + } else { + O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n" + << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; } - O << "0\n" - << " };\n" - << "\n"; - - O << " const char *Strs =\n"; - StringTable.EmitString(O); - O << ";\n"; - - O << " return Strs+InstAsmOffset[Opcode];\n" - << "}\n\n#endif\n"; + O << "}\n"; } namespace { - -/// SubtargetFeatureInfo - Helper class for storing information on a subtarget -/// feature which participates in instruction matching. -struct SubtargetFeatureInfo { - /// \brief The predicate record for this feature. - const Record *TheDef; - - /// \brief An unique index assigned to represent this feature. - unsigned Index; - - SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} - - /// \brief The name of the enumerated constant identifying this feature. - std::string getEnumName() const { - return "Feature_" + TheDef->getName(); - } -}; - -struct AsmWriterInfo { - /// Map of Predicate records to their subtarget information. - std::map SubtargetFeatures; - - /// getSubtargetFeature - Lookup or create the subtarget feature info for the - /// given operand. - SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const { - assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); - std::map::const_iterator I = - SubtargetFeatures.find(Def); - return I == SubtargetFeatures.end() ? 0 : I->second; - } - - void addReqFeatures(const std::vector &Features) { - for (std::vector::const_iterator - I = Features.begin(), E = Features.end(); I != E; ++I) { - const Record *Pred = *I; - - // Ignore predicates that are not intended for the assembler. - if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) - continue; - - if (Pred->getName().empty()) - throw TGError(Pred->getLoc(), "Predicate has no name!"); - - // Don't add the predicate again. - if (getSubtargetFeature(Pred)) - continue; - - unsigned FeatureNo = SubtargetFeatures.size(); - SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); - assert(FeatureNo < 32 && "Too many subtarget features!"); - } - } - - const SubtargetFeatureInfo *getFeatureInfo(const Record *R) { - return SubtargetFeatures[R]; - } -}; - // IAPrinter - Holds information about an InstAlias. Two InstAliases match if // they both have the same conditionals. In which case, we cannot print out the // alias for that pattern. class IAPrinter { - AsmWriterInfo &AWI; std::vector Conds; - std::map OpMap; + std::map> OpMap; + SmallVector ReqFeatures; + std::string Result; std::string AsmString; - std::vector ReqFeatures; public: - IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS) - : AWI(Info), Result(R), AsmString(AS) {} + IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {} void addCond(const std::string &C) { Conds.push_back(C); } - void addReqFeatures(const std::vector &Features) { - AWI.addReqFeatures(Features); - ReqFeatures = Features; + + void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { + assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); + assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && + "Idx out of range"); + OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); } - void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } - unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } + int getOpIndex(StringRef Op) { return OpMap[Op].first; } + std::pair &getOpData(StringRef Op) { return OpMap[Op]; } + + std::pair parseName(StringRef::iterator Start, + StringRef::iterator End) { + StringRef::iterator I = Start; + StringRef::iterator Next; + if (*I == '{') { + // ${some_name} + Start = ++I; + while (I != End && *I != '}') + ++I; + Next = I; + // eat the final '}' + if (Next != End) + ++Next; + } else { + // $name, just eat the usual suspects. + while (I != End && + ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || + (*I >= '0' && *I <= '9') || *I == '_')) + ++I; + Next = I; + } - bool print(raw_ostream &O) { + return std::make_pair(StringRef(Start, I - Start), Next); + } + + void print(raw_ostream &O) { if (Conds.empty() && ReqFeatures.empty()) { O.indent(6) << "return true;\n"; - return false; + return; } O << "if ("; @@ -643,394 +691,428 @@ public: O << *I; } - if (!ReqFeatures.empty()) { - if (Conds.begin() != Conds.end()) { - O << " &&\n"; - O.indent(8); - } else { - O << "if ("; - } - - std::string Req; - raw_string_ostream ReqO(Req); + O << ") {\n"; + O.indent(6) << "// " << Result << "\n"; - for (std::vector::iterator - I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) { - if (I != ReqFeatures.begin()) ReqO << " | "; - ReqO << AWI.getFeatureInfo(*I)->getEnumName(); + // Directly mangle mapped operands into the string. Each operand is + // identified by a '$' sign followed by a byte identifying the number of the + // operand. We add one to the index to avoid zero bytes. + StringRef ASM(AsmString); + SmallString<128> OutString; + raw_svector_ostream OS(OutString); + for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { + OS << *I; + if (*I == '$') { + StringRef Name; + std::tie(Name, I) = parseName(++I, E); + assert(isOpMapped(Name) && "Unmapped operand!"); + + int OpIndex, PrintIndex; + std::tie(OpIndex, PrintIndex) = getOpData(Name); + if (PrintIndex == -1) { + // Can use the default printOperand route. + OS << format("\\x%02X", (unsigned char)OpIndex + 1); + } else + // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand + // number, and which of our pre-detected Methods to call. + OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); + } else { + ++I; } - - O << "(AvailableFeatures & (" << ReqO.str() << ")) == (" - << ReqO.str() << ')'; } - O << ") {\n"; - O.indent(6) << "// " << Result << "\n"; - O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; - - for (std::map::iterator - I = OpMap.begin(), E = OpMap.end(); I != E; ++I) - O.indent(6) << "OpMap[\"" << I->first << "\"] = " - << I->second << ";\n"; + // Emit the string. + O.indent(6) << "AsmString = \"" << OutString << "\";\n"; O.indent(6) << "break;\n"; O.indent(4) << '}'; - return !ReqFeatures.empty(); } - bool operator==(const IAPrinter &RHS) { + bool operator==(const IAPrinter &RHS) const { if (Conds.size() != RHS.Conds.size()) return false; unsigned Idx = 0; - for (std::vector::iterator - I = Conds.begin(), E = Conds.end(); I != E; ++I) - if (*I != RHS.Conds[Idx++]) + for (const auto &str : Conds) + if (str != RHS.Conds[Idx++]) return false; return true; } - - bool operator()(const IAPrinter &RHS) { - if (Conds.size() < RHS.Conds.size()) - return true; - - unsigned Idx = 0; - for (std::vector::iterator - I = Conds.begin(), E = Conds.end(); I != E; ++I) - if (*I != RHS.Conds[Idx++]) - return *I < RHS.Conds[Idx++]; - - return false; - } }; } // end anonymous namespace -/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag -/// definitions. -static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info, - raw_ostream &O) { - O << "namespace {\n\n"; - O << "// Flags for subtarget features that participate in " - << "alias instruction matching.\n"; - O << "enum SubtargetFeatureFlag {\n"; - - for (std::map::const_iterator - I = Info.SubtargetFeatures.begin(), - E = Info.SubtargetFeatures.end(); I != E; ++I) { - SubtargetFeatureInfo &SFI = *I->second; - O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; - } +static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { + std::string FlatAsmString = + CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); + AsmString = FlatAsmString; - O << " Feature_None = 0\n"; - O << "};\n\n"; - O << "} // end anonymous namespace\n\n"; + return AsmString.count(' ') + AsmString.count('\t'); } -/// EmitComputeAvailableFeatures - Emit the function to compute the list of -/// available features given a subtarget. -static void EmitComputeAvailableFeatures(AsmWriterInfo &Info, - Record *AsmWriter, - CodeGenTarget &Target, - raw_ostream &O) { - std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - - O << "unsigned " << Target.getName() << ClassName << "::\n" - << "ComputeAvailableFeatures(const " << Target.getName() - << "Subtarget *Subtarget) const {\n"; - O << " unsigned Features = 0;\n"; - - for (std::map::const_iterator - I = Info.SubtargetFeatures.begin(), - E = Info.SubtargetFeatures.end(); I != E; ++I) { - SubtargetFeatureInfo &SFI = *I->second; - O << " if (" << SFI.TheDef->getValueAsString("CondString") - << ")\n"; - O << " Features |= " << SFI.getEnumName() << ";\n"; - } - - O << " return Features;\n"; - O << "}\n\n"; -} - -void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) { - CodeGenTarget Target(Records); - - // Enumerate the register classes. - const std::vector &RegisterClasses = - Target.getRegisterClasses(); - - O << "namespace { // Register classes\n"; - O << " enum RegClass {\n"; - - // Emit the register enum value for each RegisterClass. - for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { - if (I != 0) O << ",\n"; - O << " RC_" << RegisterClasses[I].TheDef->getName(); - } - - O << "\n };\n"; - O << "} // end anonymous namespace\n\n"; - - // Emit a function that returns 'true' if a regsiter is part of a particular - // register class. I.e., RAX is part of GR64 on X86. - O << "static bool regIsInRegisterClass" - << "(unsigned RegClass, unsigned Reg) {\n"; - - // Emit the switch that checks if a register belongs to a particular register - // class. - O << " switch (RegClass) {\n"; - O << " default: break;\n"; - - for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { - const CodeGenRegisterClass &RC = RegisterClasses[I]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); - O << " case RC_" << Name << ":\n"; - - // Emit the register list now. - unsigned IE = RC.Elements.size(); - if (IE == 1) { - O << " if (Reg == " << getQualifiedName(RC.Elements[0]) << ")\n"; - O << " return true;\n"; - } else { - O << " switch (Reg) {\n"; - O << " default: break;\n"; - - for (unsigned II = 0; II != IE; ++II) { - Record *Reg = RC.Elements[II]; - O << " case " << getQualifiedName(Reg) << ":\n"; - } - - O << " return true;\n"; - O << " }\n"; +namespace { +struct AliasPriorityComparator { + typedef std::pair ValueType; + bool operator()(const ValueType &LHS, const ValueType &RHS) { + if (LHS.second == RHS.second) { + // We don't actually care about the order, but for consistency it + // shouldn't depend on pointer comparisons. + return LHS.first.TheDef->getName() < RHS.first.TheDef->getName(); } - O << " break;\n"; + // Aliases with larger priorities should be considered first. + return LHS.second > RHS.second; } - - O << " }\n\n"; - O << " return false;\n"; - O << "}\n\n"; +}; } + void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { - CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); O << "\n#ifdef PRINT_ALIAS_INSTR\n"; O << "#undef PRINT_ALIAS_INSTR\n\n"; - EmitRegIsInRegClass(O); + ////////////////////////////// + // Gather information about aliases we need to print + ////////////////////////////// // Emit the method that prints the alias instruction. std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - - bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); - const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr"; + unsigned Variant = AsmWriter->getValueAsInt("Variant"); + unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); std::vector AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); // Create a map from the qualified name to a list of potential matches. - std::map > AliasMap; - for (std::vector::iterator - I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { - CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target); - const Record *R = *I; - if (!R->getValueAsBit("EmitAlias")) - continue; // We were told not to emit the alias, but to emit the aliasee. + typedef std::set, AliasPriorityComparator> + AliasWithPriority; + std::map AliasMap; + for (Record *R : AllInstAliases) { + int Priority = R->getValueAsInt("EmitPriority"); + if (Priority < 1) + continue; // Aliases with priority 0 are never emitted. + const DagInit *DI = R->getValueAsDag("ResultInst"); - const DefInit *Op = dynamic_cast(DI->getOperator()); - AliasMap[getQualifiedName(Op->getDef())].push_back(Alias); + const DefInit *Op = cast(DI->getOperator()); + AliasMap[getQualifiedName(Op->getDef())].insert( + std::make_pair(CodeGenInstAlias(R, Variant, Target), Priority)); } // A map of which conditions need to be met for each instruction operand // before it can be matched to the mnemonic. - std::map > IAPrinterMap; - AsmWriterInfo AWI; + std::map> IAPrinterMap; + + // A list of MCOperandPredicates for all operands in use, and the reverse map + std::vector MCOpPredicates; + DenseMap MCOpPredicateMap; - for (std::map >::iterator - I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { - std::vector &Aliases = I->second; + for (auto &Aliases : AliasMap) { + for (auto &Alias : Aliases.second) { + const CodeGenInstAlias &CGA = Alias.first; + unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); + unsigned NumResultOps = + CountNumOperands(CGA.ResultInst->AsmString, Variant); - for (std::vector::iterator - II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) { - const CodeGenInstAlias *CGA = *II; - IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(), - CGA->AsmString); + // Don't emit the alias if it has more operands than what it's aliasing. + if (NumResultOps < CountNumOperands(CGA.AsmString, Variant)) + continue; - IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates")); + IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); - unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); + unsigned NumMIOps = 0; + for (auto &Operand : CGA.ResultOperands) + NumMIOps += Operand.getMINumOperands(); std::string Cond; - Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); - IAP->addCond(Cond); + Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); + IAP.addCond(Cond); - std::map OpMap; bool CantHandle = false; + unsigned MIOpNum = 0; for (unsigned i = 0, e = LastOpNo; i != e; ++i) { - const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; + std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; + + const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; switch (RO.Kind) { - default: assert(0 && "unexpected InstAlias operand kind"); case CodeGenInstAlias::ResultOperand::K_Record: { const Record *Rec = RO.getRecord(); StringRef ROName = RO.getName(); + int PrintMethodIdx = -1; + + // These two may have a PrintMethod, which we want to record (if it's + // the first time we've seen it) and provide an index for the aliasing + // code to use. + if (Rec->isSubClassOf("RegisterOperand") || + Rec->isSubClassOf("Operand")) { + std::string PrintMethod = Rec->getValueAsString("PrintMethod"); + if (PrintMethod != "" && PrintMethod != "printOperand") { + PrintMethodIdx = std::find(PrintMethods.begin(), + PrintMethods.end(), PrintMethod) - + PrintMethods.begin(); + if (static_cast(PrintMethodIdx) == PrintMethods.size()) + PrintMethods.push_back(PrintMethod); + } + } + if (Rec->isSubClassOf("RegisterOperand")) + Rec = Rec->getValueAsDef("RegClass"); if (Rec->isSubClassOf("RegisterClass")) { - Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()"; - IAP->addCond(Cond); - - if (!IAP->isOpMapped(ROName)) { - IAP->addOperand(ROName, i); - Cond = std::string("regIsInRegisterClass(RC_") + - CGA->ResultOperands[i].getRecord()->getName() + - ", MI->getOperand(" + llvm::utostr(i) + ").getReg())"; - IAP->addCond(Cond); + IAP.addCond(Op + ".isReg()"); + + if (!IAP.isOpMapped(ROName)) { + IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); + Record *R = CGA.ResultOperands[i].getRecord(); + if (R->isSubClassOf("RegisterOperand")) + R = R->getValueAsDef("RegClass"); + Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + + R->getName() + "RegClassID)" + ".contains(" + Op + ".getReg())"; } else { - Cond = std::string("MI->getOperand(") + - llvm::utostr(i) + ").getReg() == MI->getOperand(" + - llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; - IAP->addCond(Cond); + Cond = Op + ".getReg() == MI->getOperand(" + + llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()"; } } else { - assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); - // FIXME: We need to handle these situations. - delete IAP; - IAP = 0; - CantHandle = true; - break; + // Assume all printable operands are desired for now. This can be + // overridden in the InstAlias instantiation if necessary. + IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); + + // There might be an additional predicate on the MCOperand + unsigned Entry = MCOpPredicateMap[Rec]; + if (!Entry) { + if (!Rec->isValueUnset("MCOperandPredicate")) { + MCOpPredicates.push_back(Rec); + Entry = MCOpPredicates.size(); + MCOpPredicateMap[Rec] = Entry; + } else + break; // No conditions on this operand at all + } + Cond = Target.getName() + ClassName + "ValidateMCOperand(" + + Op + ", STI, " + llvm::utostr(Entry) + ")"; } - + // for all subcases of ResultOperand::K_Record: + IAP.addCond(Cond); break; } - case CodeGenInstAlias::ResultOperand::K_Imm: - Cond = std::string("MI->getOperand(") + - llvm::utostr(i) + ").getImm() == " + - llvm::utostr(CGA->ResultOperands[i].getImm()); - IAP->addCond(Cond); + case CodeGenInstAlias::ResultOperand::K_Imm: { + // Just because the alias has an immediate result, doesn't mean the + // MCInst will. An MCExpr could be present, for example. + IAP.addCond(Op + ".isImm()"); + + Cond = Op + ".getImm() == " + + llvm::utostr(CGA.ResultOperands[i].getImm()); + IAP.addCond(Cond); break; + } case CodeGenInstAlias::ResultOperand::K_Reg: - Cond = std::string("MI->getOperand(") + - llvm::utostr(i) + ").getReg() == " + Target.getName() + - "::" + CGA->ResultOperands[i].getRegister()->getName(); - IAP->addCond(Cond); + // If this is zero_reg, something's playing tricks we're not + // equipped to handle. + if (!CGA.ResultOperands[i].getRegister()) { + CantHandle = true; + break; + } + + Cond = Op + ".getReg() == " + Target.getName() + "::" + + CGA.ResultOperands[i].getRegister()->getName(); + IAP.addCond(Cond); break; } - if (!IAP) break; + MIOpNum += RO.getMINumOperands(); } if (CantHandle) continue; - IAPrinterMap[I->first].push_back(IAP); + IAPrinterMap[Aliases.first].push_back(std::move(IAP)); } } - EmitSubtargetFeatureFlagEnumeration(AWI, O); - EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O); + ////////////////////////////// + // Write out the printAliasInstr function + ////////////////////////////// - O << "bool " << Target.getName() << ClassName - << "::printAliasInstr(const " << MachineInstrClassName - << " *MI, raw_ostream &OS) {\n"; + std::string Header; + raw_string_ostream HeaderO(Header); + + HeaderO << "bool " << Target.getName() << ClassName + << "::printAliasInstr(const MCInst" + << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") + << "raw_ostream &OS) {\n"; std::string Cases; raw_string_ostream CasesO(Cases); - bool NeedAvailableFeatures = false; - for (std::map >::iterator - I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { - std::vector &IAPs = I->second; + for (auto &Entry : IAPrinterMap) { + std::vector &IAPs = Entry.second; std::vector UniqueIAPs; - for (std::vector::iterator - II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { - IAPrinter *LHS = *II; + for (auto &LHS : IAPs) { bool IsDup = false; - for (std::vector::iterator - III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { - IAPrinter *RHS = *III; - if (LHS != RHS && *LHS == *RHS) { + for (const auto &RHS : IAPs) { + if (&LHS != &RHS && LHS == RHS) { IsDup = true; break; } } - if (!IsDup) UniqueIAPs.push_back(LHS); + if (!IsDup) + UniqueIAPs.push_back(&LHS); } if (UniqueIAPs.empty()) continue; - CasesO.indent(2) << "case " << I->first << ":\n"; + CasesO.indent(2) << "case " << Entry.first << ":\n"; - for (std::vector::iterator - II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { - IAPrinter *IAP = *II; + for (IAPrinter *IAP : UniqueIAPs) { CasesO.indent(4); - NeedAvailableFeatures |= IAP->print(CasesO); + IAP->print(CasesO); CasesO << '\n'; } - CasesO.indent(4) << "return true;\n"; + CasesO.indent(4) << "return false;\n"; } - if (CasesO.str().empty() || !isMC) { - O << " return true;\n"; + if (CasesO.str().empty()) { + O << HeaderO.str(); + O << " return false;\n"; O << "}\n\n"; O << "#endif // PRINT_ALIAS_INSTR\n"; return; } - O.indent(2) << "StringRef AsmString;\n"; - O.indent(2) << "std::map OpMap;\n"; - if (NeedAvailableFeatures) - O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n"; + if (!MCOpPredicates.empty()) + O << "static bool " << Target.getName() << ClassName + << "ValidateMCOperand(const MCOperand &MCOp,\n" + << " const MCSubtargetInfo &STI,\n" + << " unsigned PredicateIndex);\n"; + + O << HeaderO.str(); + O.indent(2) << "const char *AsmString;\n"; O.indent(2) << "switch (MI->getOpcode()) {\n"; - O.indent(2) << "default: return true;\n"; + O.indent(2) << "default: return false;\n"; O << CasesO.str(); O.indent(2) << "}\n\n"; // Code that prints the alias, replacing the operands with the ones from the // MCInst. - O << " std::pair ASM = AsmString.split(' ');\n"; - O << " OS << '\\t' << ASM.first;\n"; + O << " unsigned I = 0;\n"; + O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n"; + O << " AsmString[I] != '\\0')\n"; + O << " ++I;\n"; + O << " OS << '\\t' << StringRef(AsmString, I);\n"; - O << " if (!ASM.second.empty()) {\n"; + O << " if (AsmString[I] != '\\0') {\n"; O << " OS << '\\t';\n"; - O << " for (StringRef::iterator\n"; - O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n"; - O << " if (*I == '$') {\n"; - O << " StringRef::iterator Start = ++I;\n"; - O << " while (I != E &&\n"; - O << " ((*I >= 'a' && *I <= 'z') ||\n"; - O << " (*I >= 'A' && *I <= 'Z') ||\n"; - O << " (*I >= '0' && *I <= '9') ||\n"; - O << " *I == '_'))\n"; + O << " do {\n"; + O << " if (AsmString[I] == '$') {\n"; + O << " ++I;\n"; + O << " if (AsmString[I] == (char)0xff) {\n"; O << " ++I;\n"; - O << " StringRef Name(Start, I - Start);\n"; - O << " printOperand(MI, OpMap[Name], OS);\n"; + O << " int OpIdx = AsmString[I++] - 1;\n"; + O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; + O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; + O << (PassSubtarget ? "STI, " : ""); + O << "OS);\n"; + O << " } else\n"; + O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; + O << (PassSubtarget ? "STI, " : ""); + O << "OS);\n"; O << " } else {\n"; - O << " OS << *I++;\n"; + O << " OS << AsmString[I++];\n"; O << " }\n"; - O << " }\n"; + O << " } while (AsmString[I] != '\\0');\n"; O << " }\n\n"; - - O << " return false;\n"; + + O << " return true;\n"; + O << "}\n\n"; + + ////////////////////////////// + // Write out the printCustomAliasOperand function + ////////////////////////////// + + O << "void " << Target.getName() << ClassName << "::" + << "printCustomAliasOperand(\n" + << " const MCInst *MI, unsigned OpIdx,\n" + << " unsigned PrintMethodIdx,\n" + << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") + << " raw_ostream &OS) {\n"; + if (PrintMethods.empty()) + O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; + else { + O << " switch (PrintMethodIdx) {\n" + << " default:\n" + << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" + << " break;\n"; + + for (unsigned i = 0; i < PrintMethods.size(); ++i) { + O << " case " << i << ":\n" + << " " << PrintMethods[i] << "(MI, OpIdx, " + << (PassSubtarget ? "STI, " : "") << "OS);\n" + << " break;\n"; + } + O << " }\n"; + } O << "}\n\n"; + if (!MCOpPredicates.empty()) { + O << "static bool " << Target.getName() << ClassName + << "ValidateMCOperand(const MCOperand &MCOp,\n" + << " const MCSubtargetInfo &STI,\n" + << " unsigned PredicateIndex) {\n" + << " switch (PredicateIndex) {\n" + << " default:\n" + << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" + << " break;\n"; + + for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { + Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate"); + if (StringInit *SI = dyn_cast(MCOpPred)) { + O << " case " << i + 1 << ": {\n" + << SI->getValue() << "\n" + << " }\n"; + } else + llvm_unreachable("Unexpected MCOperandPredicate field!"); + } + O << " }\n" + << "}\n\n"; + } + O << "#endif // PRINT_ALIAS_INSTR\n"; } -void AsmWriterEmitter::run(raw_ostream &O) { - EmitSourceFileHeader("Assembly Writer Source Fragment", O); +AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { + Record *AsmWriter = Target.getAsmWriter(); + unsigned Variant = AsmWriter->getValueAsInt("Variant"); + unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); + for (const CodeGenInstruction *I : Target.instructions()) + if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") + Instructions.emplace_back(*I, Variant, PassSubtarget); + + // Get the instruction numbering. + NumberedInstructions = &Target.getInstructionsByEnumValue(); + + // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not + // all machine instructions are necessarily being printed, so there may be + // target instructions not in this map. + for (AsmWriterInst &AWI : Instructions) + CGIAWIMap.insert(std::make_pair(AWI.CGI, &AWI)); +} +void AsmWriterEmitter::run(raw_ostream &O) { EmitPrintInstruction(O); EmitGetRegisterName(O); - EmitGetInstructionName(O); EmitPrintAliasInstruction(O); } + +namespace llvm { + +void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Assembly Writer Source Fragment", OS); + AsmWriterEmitter(RK).run(OS); +} + +} // End llvm namespace