X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FTransforms%2FInstCombine%2For.ll;h=c0bb28d15ccf48723628bafa9cfab2f54955742a;hb=2920a71663b96f2c33b1fee09ca5ca9f5dc1cf12;hp=822dfb3d55073066b4c0964ce6d1c88c98a08994;hpb=e4412c1f0b636980d77a518b76e94559830eeaed;p=oota-llvm.git diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll index 822dfb3d550..c0bb28d15cc 100644 --- a/test/Transforms/InstCombine/or.ll +++ b/test/Transforms/InstCombine/or.ll @@ -126,8 +126,8 @@ define i1 @test14(i32 %A, i32 %B) { %D = or i1 %C1, %C2 ret i1 %D ; CHECK: @test14 -; CHECK: %D = icmp ne i32 %A, %B -; CHECK: ret i1 %D +; CHECK: icmp ne i32 %A, %B +; CHECK: ret i1 } define i1 @test15(i32 %A, i32 %B) { @@ -137,8 +137,8 @@ define i1 @test15(i32 %A, i32 %B) { %D = or i1 %C1, %C2 ret i1 %D ; CHECK: @test15 -; CHECK: %D = icmp ule i32 %A, %B -; CHECK: ret i1 %D +; CHECK: icmp ule i32 %A, %B +; CHECK: ret i1 } define i32 @test16(i32 %A) { @@ -171,8 +171,8 @@ define i1 @test18(i32 %A) { ret i1 %D ; CHECK: @test18 ; CHECK: add i32 -; CHECK: %D = icmp ugt -; CHECK: ret i1 %D +; CHECK: icmp ugt +; CHECK: ret i1 } define i1 @test19(i32 %A) { @@ -183,8 +183,8 @@ define i1 @test19(i32 %A) { ret i1 %D ; CHECK: @test19 ; CHECK: add i32 -; CHECK: %D = icmp ult -; CHECK: ret i1 %D +; CHECK: icmp ult +; CHECK: ret i1 } define i32 @test20(i32 %x) { @@ -236,8 +236,8 @@ define i1 @test24(double %X, double %Y) { ret i1 %bothcond ; CHECK: @test24 -; CHECK: %bothcond = fcmp uno double %Y, %X ; [#uses=1] -; CHECK: ret i1 %bothcond +; CHECK: = fcmp uno double %Y, %X +; CHECK: ret i1 } ; PR3266 & PR5276 @@ -316,7 +316,96 @@ entry: %E = or i32 %D, %C ret i32 %E ; CHECK: @test30 -; CHECK: %B = or i32 %A, 32962 -; CHECK: %E = and i32 %B, -25350 +; CHECK: %D = and i32 %A, -58312 +; CHECK: %E = or i32 %D, 32962 ; CHECK: ret i32 %E } + +; PR4216 +define i64 @test31(i64 %A) nounwind readnone ssp noredzone { + %B = or i64 %A, 194 + %D = and i64 %B, 250 + + %C = or i64 %A, 32768 + %E = and i64 %C, 4294941696 + + %F = or i64 %D, %E + ret i64 %F +; CHECK: @test31 +; CHECK-NEXT: %E = and i64 %A, 4294908984 +; CHECK-NEXT: %F = or i64 %E, 32962 +; CHECK-NEXT: ret i64 %F +} + +define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191) { + %and.i135 = sext <4 x i1> %and.i1352 to <4 x i32> ; <<4 x i32>> [#uses=2] + %and.i129 = and <4 x i32> %vecinit6.i176, %and.i135 ; <<4 x i32>> [#uses=1] + %neg.i = xor <4 x i32> %and.i135, ; <<4 x i32>> [#uses=1] + %and.i = and <4 x i32> %vecinit6.i191, %neg.i ; <<4 x i32>> [#uses=1] + %or.i = or <4 x i32> %and.i, %and.i129 ; <<4 x i32>> [#uses=1] + ret <4 x i32> %or.i +; Don't turn this into a vector select until codegen matures to handle them +; better. +; CHECK: @test32 +; CHECK: or <4 x i32> %and.i, %and.i129 +} + +define i1 @test33(i1 %X, i1 %Y) { + %a = or i1 %X, %Y + %b = or i1 %a, %X + ret i1 %b +; CHECK: @test33 +; CHECK-NEXT: or i1 %X, %Y +; CHECK-NEXT: ret +} + +define i32 @test34(i32 %X, i32 %Y) { + %a = or i32 %X, %Y + %b = or i32 %Y, %a + ret i32 %b +; CHECK: @test34 +; CHECK-NEXT: or i32 %X, %Y +; CHECK-NEXT: ret +} + +define i32 @test35(i32 %a, i32 %b) { + %1 = or i32 %a, 1135 + %2 = or i32 %1, %b + ret i32 %2 + ; CHECK: @test35 + ; CHECK-NEXT: or i32 %a, %b + ; CHECK-NEXT: or i32 %1, 1135 +} + +define i1 @test36(i32 %x) { + %cmp1 = icmp eq i32 %x, 23 + %cmp2 = icmp eq i32 %x, 24 + %ret1 = or i1 %cmp1, %cmp2 + %cmp3 = icmp eq i32 %x, 25 + %ret2 = or i1 %ret1, %cmp3 + ret i1 %ret2 +; CHECK: @test36 +; CHECK-NEXT: %x.off = add i32 %x, -23 +; CHECK-NEXT: icmp ult i32 %x.off, 3 +; CHECK-NEXT: ret i1 +} + +define i32 @test37(i32* %xp, i32 %y) { +; CHECK: @test37 +; CHECK: select i1 %tobool, i32 -1, i32 %x + %tobool = icmp ne i32 %y, 0 + %sext = sext i1 %tobool to i32 + %x = load i32* %xp + %or = or i32 %sext, %x + ret i32 %or +} + +define i32 @test38(i32* %xp, i32 %y) { +; CHECK: @test38 +; CHECK: select i1 %tobool, i32 -1, i32 %x + %tobool = icmp ne i32 %y, 0 + %sext = sext i1 %tobool to i32 + %x = load i32* %xp + %or = or i32 %x, %sext + ret i32 %or +}