X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FX86%2Fcrash.ll;h=ee73377dffde4fb8c721a15fdc051b67e95da06c;hb=4a524934577d85e5095df8ea62ad6a3261076d0c;hp=153145728f5896edbdb897fc23bfc13a1833599c;hpb=dee83c90bb7bda57f6d0db2d8f9138f411ecdbbc;p=oota-llvm.git diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 153145728f5..ee73377dffd 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -1,21 +1,22 @@ -; RUN: llc -march=x86 %s -o - -; RUN: llc -march=x86-64 %s -o - - +; REQUIRES: asserts +; RUN: llc -march=x86 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness +; RUN: llc -march=x86-64 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness + ; PR6497 ; Chain and flag folding issues. define i32 @test1() nounwind ssp { entry: - %tmp5.i = volatile load i32* undef ; [#uses=1] + %tmp5.i = load volatile i32* undef ; [#uses=1] %conv.i = zext i32 %tmp5.i to i64 ; [#uses=1] - %tmp12.i = volatile load i32* undef ; [#uses=1] + %tmp12.i = load volatile i32* undef ; [#uses=1] %conv13.i = zext i32 %tmp12.i to i64 ; [#uses=1] %shl.i = shl i64 %conv13.i, 32 ; [#uses=1] %or.i = or i64 %shl.i, %conv.i ; [#uses=1] %add16.i = add i64 %or.i, 256 ; [#uses=1] %shr.i = lshr i64 %add16.i, 8 ; [#uses=1] %conv19.i = trunc i64 %shr.i to i32 ; [#uses=1] - volatile store i32 %conv19.i, i32* undef + store volatile i32 %conv19.i, i32* undef ret i32 undef } @@ -107,8 +108,8 @@ do.body92: ; preds = %if.then66 ret void } -!0 = metadata !{i32 633550} -!1 = metadata !{i32 634261} +!0 = metadata !{i32 633550} +!1 = metadata !{i32 634261} ; Crash during XOR optimization. @@ -203,7 +204,7 @@ entry: ; define fastcc void @func_61() nounwind sspreq { entry: - %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false) + %t1 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false) %t2 = icmp eq i64 %t1, -1 br i1 %t2, label %bb2, label %bb1 @@ -214,7 +215,7 @@ bb2: ret void } -declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone +declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) nounwind readnone ; PR10277 ; This test has dead code elimination caused by remat during spilling. @@ -238,7 +239,7 @@ declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { bb: - %tmp = load %t9** undef, align 4, !tbaa !0 + %tmp = load %t9** undef, align 4 %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 br label %bb4 @@ -391,3 +392,201 @@ if.end: %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind ret void } + +; Avoid emitting wrong kill flags from InstrEmitter. +; InstrEmitter::EmitSubregNode() may steal virtual registers from already +; emitted blocks when isCoalescableExtInstr points out the opportunity. +; Make sure kill flags are cleared on the newly global virtual register. +define i64 @ov_read(i8* %vf, i8* nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, i32* %bitstream) nounwind uwtable ssp { +entry: + br i1 undef, label %return, label %while.body.preheader + +while.body.preheader: ; preds = %entry + br i1 undef, label %if.then3, label %if.end7 + +if.then3: ; preds = %while.body.preheader + %0 = load i32* undef, align 4 + br i1 undef, label %land.lhs.true.i255, label %if.end7 + +land.lhs.true.i255: ; preds = %if.then3 + br i1 undef, label %if.then.i256, label %if.end7 + +if.then.i256: ; preds = %land.lhs.true.i255 + %sub.i = sub i32 0, %0 + %conv = sext i32 %sub.i to i64 + br i1 undef, label %if.end7, label %while.end + +if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader + unreachable + +while.end: ; preds = %if.then.i256 + %cmp18 = icmp sgt i32 %sub.i, 0 + %.conv = select i1 %cmp18, i64 -131, i64 %conv + ret i64 %.conv + +return: ; preds = %entry + ret i64 -131 +} + +; The tail call to a varargs function sets %AL. +; uitofp expands to an FCMOV instruction which splits the basic block. +; Make sure the live range of %AL isn't split. +@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32 +define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 { +entry: + %x7 = load i64* %this, align 8 + %sub = add i64 %x7, -1 + %conv = uitofp i64 %sub to float + %div = fmul float %conv, 5.000000e-01 + %conv2 = fpext float %div to double + tail call void (...)* @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2) + ret void +} +declare void @_Z6PrintFz(...) + +@a = external global i32, align 4 +@fn1.g = private unnamed_addr constant [9 x i32*] [i32* null, i32* @a, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null], align 16 +@e = external global i32, align 4 + +define void @pr13943() nounwind uwtable ssp { +entry: + %srcval = load i576* bitcast ([9 x i32*]* @fn1.g to i576*), align 16 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %g.0 = phi i576 [ %srcval, %entry ], [ %ins, %for.inc ] + %0 = load i32* @e, align 4 + %1 = lshr i576 %g.0, 64 + %2 = trunc i576 %1 to i64 + %3 = inttoptr i64 %2 to i32* + %cmp = icmp eq i32* undef, %3 + %conv2 = zext i1 %cmp to i32 + %and = and i32 %conv2, %0 + tail call void (...)* @fn3(i32 %and) nounwind + %tobool = icmp eq i32 undef, 0 + br i1 %tobool, label %for.inc, label %if.then + +if.then: ; preds = %for.cond + ret void + +for.inc: ; preds = %for.cond + %4 = shl i576 %1, 384 + %mask = and i576 %g.0, -726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307841 + %5 = and i576 %4, 726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307840 + %ins = or i576 %5, %mask + br label %for.cond +} + +declare void @fn3(...) + +; Check coalescing of IMPLICIT_DEF instructions: +; +; %vreg1 = IMPLICIT_DEF +; %vreg2 = MOV32r0 +; +; When coalescing %vreg1 and %vreg2, the IMPLICIT_DEF instruction should be +; erased along with its value number. +; +define void @rdar12474033() nounwind ssp { +bb: + br i1 undef, label %bb21, label %bb1 + +bb1: ; preds = %bb + switch i32 undef, label %bb10 [ + i32 4, label %bb2 + i32 1, label %bb9 + i32 5, label %bb3 + i32 6, label %bb3 + i32 2, label %bb9 + ] + +bb2: ; preds = %bb1 + unreachable + +bb3: ; preds = %bb1, %bb1 + br i1 undef, label %bb4, label %bb5 + +bb4: ; preds = %bb3 + unreachable + +bb5: ; preds = %bb3 + %tmp = load <4 x float>* undef, align 1 + %tmp6 = bitcast <4 x float> %tmp to i128 + %tmp7 = load <4 x float>* undef, align 1 + %tmp8 = bitcast <4 x float> %tmp7 to i128 + br label %bb10 + +bb9: ; preds = %bb1, %bb1 + unreachable + +bb10: ; preds = %bb5, %bb1 + %tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ] + %tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ] + switch i32 undef, label %bb21 [ + i32 2, label %bb18 + i32 3, label %bb13 + i32 5, label %bb16 + i32 6, label %bb17 + i32 1, label %bb18 + ] + +bb13: ; preds = %bb10 + br i1 undef, label %bb15, label %bb14 + +bb14: ; preds = %bb13 + br label %bb21 + +bb15: ; preds = %bb13 + unreachable + +bb16: ; preds = %bb10 + unreachable + +bb17: ; preds = %bb10 + unreachable + +bb18: ; preds = %bb10, %bb10 + %tmp19 = bitcast i128 %tmp11 to <4 x float> + %tmp20 = bitcast i128 %tmp12 to <4 x float> + br label %bb21 + +bb21: ; preds = %bb18, %bb14, %bb10, %bb + %tmp22 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp20, %bb18 ] + %tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ] + store <4 x float> %tmp23, <4 x float>* undef, align 16 + store <4 x float> %tmp22, <4 x float>* undef, align 16 + switch i32 undef, label %bb29 [ + i32 5, label %bb27 + i32 1, label %bb24 + i32 2, label %bb25 + i32 14, label %bb28 + i32 4, label %bb26 + ] + +bb24: ; preds = %bb21 + unreachable + +bb25: ; preds = %bb21 + br label %bb29 + +bb26: ; preds = %bb21 + br label %bb29 + +bb27: ; preds = %bb21 + unreachable + +bb28: ; preds = %bb21 + br label %bb29 + +bb29: ; preds = %bb28, %bb26, %bb25, %bb21 + unreachable +} + +define void @pr14194() nounwind uwtable { + %tmp = load i64* undef, align 16 + %tmp1 = trunc i64 %tmp to i32 + %tmp2 = lshr i64 %tmp, 32 + %tmp3 = trunc i64 %tmp2 to i32 + %tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind + ret void +}