X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FX86%2Fclz.ll;h=6a6f5256f44d78e4d17ea5387abc1a9c2a3e8032;hb=bc3868a11d27c8b9f8dee28902ee04ddf0522f05;hp=6f4d305385b6c63427d4a86d9e7b859ddbd7f97e;hpb=3d636ea8edf9332ab5ab2d92f7ea5c7444e88757;p=oota-llvm.git

diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll
index 6f4d305385b..6a6f5256f44 100644
--- a/test/CodeGen/X86/clz.ll
+++ b/test/CodeGen/X86/clz.ll
@@ -12,8 +12,8 @@ declare i64 @llvm.ctlz.i64(i64, i1)
 define i8 @cttz_i8(i8 %x)  {
   %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK: cttz_i8:
-; CHECK: bsfw
+; CHECK-LABEL: cttz_i8:
+; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
 }
@@ -21,7 +21,7 @@ define i8 @cttz_i8(i8 %x)  {
 define i16 @cttz_i16(i16 %x)  {
   %tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK: cttz_i16:
+; CHECK-LABEL: cttz_i16:
 ; CHECK: bsfw
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -30,7 +30,7 @@ define i16 @cttz_i16(i16 %x)  {
 define i32 @cttz_i32(i32 %x)  {
   %tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: cttz_i32:
+; CHECK-LABEL: cttz_i32:
 ; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -39,7 +39,7 @@ define i32 @cttz_i32(i32 %x)  {
 define i64 @cttz_i64(i64 %x)  {
   %tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: cttz_i64:
+; CHECK-LABEL: cttz_i64:
 ; CHECK: bsfq
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i8 @ctlz_i8(i8 %x) {
 entry:
   %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
   ret i8 %tmp2
-; CHECK: ctlz_i8:
+; CHECK-LABEL: ctlz_i8:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $7,
@@ -60,7 +60,7 @@ define i16 @ctlz_i16(i16 %x) {
 entry:
   %tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
   ret i16 %tmp2
-; CHECK: ctlz_i16:
+; CHECK-LABEL: ctlz_i16:
 ; CHECK: bsrw
 ; CHECK-NOT: cmov
 ; CHECK: xorl $15,
@@ -70,7 +70,7 @@ entry:
 define i32 @ctlz_i32(i32 %x) {
   %tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: ctlz_i32:
+; CHECK-LABEL: ctlz_i32:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -80,7 +80,7 @@ define i32 @ctlz_i32(i32 %x) {
 define i64 @ctlz_i64(i64 %x) {
   %tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: ctlz_i64:
+; CHECK-LABEL: ctlz_i64:
 ; CHECK: bsrq
 ; CHECK-NOT: cmov
 ; CHECK: xorq $63,
@@ -90,7 +90,7 @@ define i64 @ctlz_i64(i64 %x) {
 define i32 @ctlz_i32_cmov(i32 %n) {
 entry:
 ; Generate a cmov to handle zero inputs when necessary.
-; CHECK: ctlz_i32_cmov:
+; CHECK-LABEL: ctlz_i32_cmov:
 ; CHECK: bsrl
 ; CHECK: cmov
 ; CHECK: xorl $31,
@@ -104,7 +104,7 @@ entry:
 ; Don't generate the cmovne when the source is known non-zero (and bsr would
 ; not set ZF).
 ; rdar://9490949
-; CHECK: ctlz_i32_fold_cmov:
+; CHECK-LABEL: ctlz_i32_fold_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -118,7 +118,7 @@ define i32 @ctlz_bsr(i32 %n) {
 entry:
 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
 ; the most significant bit, which is what 'bsr' does natively.
-; CHECK: ctlz_bsr:
+; CHECK-LABEL: ctlz_bsr:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret
@@ -131,7 +131,7 @@ define i32 @ctlz_bsr_cmov(i32 %n) {
 entry:
 ; Same as ctlz_bsr, but ensure this happens even when there is a potential
 ; zero.
-; CHECK: ctlz_bsr_cmov:
+; CHECK-LABEL: ctlz_bsr_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret