X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FSPARC%2F64bit.ll;h=274fa32fad35a69e1400b8ce144d683adc8dee8a;hb=bb6f14e3581c78509405a3d415e72821db8a2066;hp=f881ddfbc06d45c3d1991ea08b6c5578b75acf65;hpb=65ca7aa57d5e9b391f02a5686e7622deaac146f9;p=oota-llvm.git

diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index f881ddfbc06..274fa32fad3 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
-; RUN: llc < %s -march=sparcv9  | FileCheck %s -check-prefix=OPT
+; RUN: llc < %s -march=sparcv9 -mattr=+popc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
+; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=OPT
 
-; CHECK: ret2:
-; CHECK: or %g0, %i1, %i0
+; CHECK-LABEL: ret2:
+; CHECK: mov %i1, %i0
 
-; OPT: ret2:
-; OPT: jmp %o7+8
-; OPT: or %g0, %o1, %o0
+; OPT-LABEL: ret2:
+; OPT: retl
+; OPT: mov %o1, %o0
 define i64 @ret2(i64 %a, i64 %b) {
   ret i64 %b
 }
@@ -14,8 +14,8 @@ define i64 @ret2(i64 %a, i64 %b) {
 ; CHECK: shl_imm
 ; CHECK: sllx %i0, 7, %i0
 
-; OPT: shl_imm:
-; OPT: jmp %o7+8
+; OPT-LABEL: shl_imm:
+; OPT: retl
 ; OPT: sllx %o0, 7, %o0
 define i64 @shl_imm(i64 %a) {
   %x = shl i64 %a, 7
@@ -25,8 +25,8 @@ define i64 @shl_imm(i64 %a) {
 ; CHECK: sra_reg
 ; CHECK: srax %i0, %i1, %i0
 
-; OPT: sra_reg:
-; OPT: jmp %o7+8
+; OPT-LABEL: sra_reg:
+; OPT: retl
 ; OPT: srax %o0, %o1, %o0
 define i64 @sra_reg(i64 %a, i64 %b) {
   %x = ashr i64 %a, %b
@@ -39,21 +39,21 @@ define i64 @sra_reg(i64 %a, i64 %b) {
 ;     restore %g0, %g0, %o0
 ;
 ; CHECK: ret_imm0
-; CHECK: or %g0, 0, %i0
+; CHECK: mov 0, %i0
 
 ; OPT: ret_imm0
-; OPT: jmp %o7+8
-; OPT: or %g0, 0, %o0
+; OPT: retl
+; OPT: mov 0, %o0
 define i64 @ret_imm0() {
   ret i64 0
 }
 
 ; CHECK: ret_simm13
-; CHECK: or %g0, -4096, %i0
+; CHECK: mov -4096, %i0
 
 ; OPT:   ret_simm13
-; OPT:   jmp %o7+8
-; OPT:   or %g0, -4096, %o0
+; OPT:   retl
+; OPT:   mov -4096, %o0
 define i64 @ret_simm13() {
   ret i64 -4096
 }
@@ -64,7 +64,7 @@ define i64 @ret_simm13() {
 ; CHECK: restore
 
 ; OPT:  ret_sethi
-; OPT:  jmp %o7+8
+; OPT:  retl
 ; OPT:  sethi 4, %o0
 define i64 @ret_sethi() {
   ret i64 4096
@@ -76,7 +76,7 @@ define i64 @ret_sethi() {
 
 ; OPT: ret_sethi_or
 ; OPT: sethi 4, [[R:%[go][0-7]]]
-; OPT: jmp %o7+8
+; OPT: retl
 ; OPT: or [[R]], 1, %o0
 
 define i64 @ret_sethi_or() {
@@ -89,7 +89,7 @@ define i64 @ret_sethi_or() {
 
 ; OPT: ret_nimm33
 ; OPT: sethi 4, [[R:%[go][0-7]]]
-; OPT: jmp %o7+8
+; OPT: retl
 ; OPT: xor [[R]], -4, %o0
 
 define i64 @ret_nimm33() {
@@ -140,17 +140,17 @@ define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
 ; CHECK: ldsh [%i3]
 ; CHECK: sth %
 define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
-  %a = load i64* %p
+  %a = load i64, i64* %p
   %ai = add i64 1, %a
   store i64 %ai, i64* %p
-  %b = load i32* %q
+  %b = load i32, i32* %q
   %b2 = zext i32 %b to i64
   %bi = trunc i64 %ai to i32
   store i32 %bi, i32* %q
-  %c = load i32* %r
+  %c = load i32, i32* %r
   %c2 = sext i32 %c to i64
   store i64 %ai, i64* %p
-  %d = load i16* %s
+  %d = load i16, i16* %s
   %d2 = sext i16 %d to i64
   %di = trunc i64 %ai to i16
   store i16 %di, i16* %s
@@ -161,6 +161,14 @@ define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
   ret i64 %x3
 }
 
+; CHECK: load_bool
+; CHECK: ldub [%i0], %i0
+define i64 @load_bool(i1* %p) {
+  %a = load i1, i1* %p
+  %b = zext i1 %a to i64
+  ret i64 %b
+}
+
 ; CHECK: stores
 ; CHECK: ldx [%i0+8], [[R:%[goli][0-7]]]
 ; CHECK: stx [[R]], [%i0+16]
@@ -168,20 +176,20 @@ define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
 ; CHECK: sth [[R]], [%i2+40]
 ; CHECK: stb [[R]], [%i3+-20]
 define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
-  %p1 = getelementptr i64* %p, i64 1
-  %p2 = getelementptr i64* %p, i64 2
-  %pv = load i64* %p1
+  %p1 = getelementptr i64, i64* %p, i64 1
+  %p2 = getelementptr i64, i64* %p, i64 2
+  %pv = load i64, i64* %p1
   store i64 %pv, i64* %p2
 
-  %q2 = getelementptr i32* %q, i32 -2
+  %q2 = getelementptr i32, i32* %q, i32 -2
   %qv = trunc i64 %pv to i32
   store i32 %qv, i32* %q2
 
-  %r2 = getelementptr i16* %r, i16 20
+  %r2 = getelementptr i16, i16* %r, i16 20
   %rv = trunc i64 %pv to i16
   store i16 %rv, i16* %r2
 
-  %s2 = getelementptr i8* %s, i8 -20
+  %s2 = getelementptr i8, i8* %s, i8 -20
   %sv = trunc i64 %pv to i8
   store i8 %sv, i8* %s2
 
@@ -192,8 +200,8 @@ define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
 ; CHECK: ldub [%i0], [[R:%[goli][0-7]]]
 ; CHECK: sll [[R]], [[R]], %i0
 define i8 @promote_shifts(i8* %p) {
-  %L24 = load i8* %p
-  %L32 = load i8* %p
+  %L24 = load i8, i8* %p
+  %L32 = load i8, i8* %p
   %B36 = shl i8 %L24, %L32
   ret i8 %B36
 }
@@ -222,7 +230,7 @@ define i64 @unsigned_divide(i64 %a, i64 %b) {
 define void @access_fi() {
 entry:
   %b = alloca [32 x i8], align 1
-  %arraydecay = getelementptr inbounds [32 x i8]* %b, i64 0, i64 0
+  %arraydecay = getelementptr inbounds [32 x i8], [32 x i8]* %b, i64 0, i64 0
   call void @g(i8* %arraydecay) #2
   ret void
 }
@@ -230,7 +238,7 @@ entry:
 declare void @g(i8*)
 
 ; CHECK: expand_setcc
-; CHECK: subcc %i0, 1,
+; CHECK: cmp %i0, 1
 ; CHECK: movl %xcc, 1,
 define i32 @expand_setcc(i64 %a) {
   %cond = icmp sle i64 %a, 0
@@ -262,3 +270,41 @@ define double @bitcast_f64_i64(i64 %x) {
   %y = bitcast i64 %x to double
   ret double %y
 }
+
+; CHECK-LABEL: store_zero:
+; CHECK: stx %g0, [%i0]
+; CHECK: stx %g0, [%i1+8]
+
+; OPT-LABEL:  store_zero:
+; OPT:  stx %g0, [%o0]
+; OPT:  stx %g0, [%o1+8]
+define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
+entry:
+  store i64 0, i64* %a, align 8
+  %0 = getelementptr inbounds i64, i64* %b, i32 1
+  store i64 0, i64* %0, align 8
+  ret i64 0
+}
+
+; CHECK-LABEL: bit_ops
+; CHECK:       popc
+
+; OPT-LABEL: bit_ops
+; OPT:       popc
+
+define i64 @bit_ops(i64 %arg) {
+entry:
+  %0 = tail call i64 @llvm.ctpop.i64(i64 %arg)
+  %1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true)
+  %2 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 true)
+  %3 = tail call i64 @llvm.bswap.i64(i64 %arg)
+  %4 = add i64 %0, %1
+  %5 = add i64 %2, %3
+  %6 = add i64 %4, %5
+  ret i64 %6
+}
+
+declare i64 @llvm.ctpop.i64(i64) nounwind readnone
+declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
+declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
+declare i64 @llvm.bswap.i64(i64) nounwind readnone