X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FMips%2Fmsa%2F3r-d.ll;h=4fc32b76a7b2b8898b0fc02418089b20faded0ab;hb=30e21e7109a6467f2c5e60521c5ec849f6aededb;hp=ee94e5650d8b56346bc30c528b7be5d3d749a845;hpb=a65f149af6fd90f1a849def3c1afb15d741ced2a;p=oota-llvm.git diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll index ee94e5650d8..4fc32b76a7b 100644 --- a/test/CodeGen/Mips/msa/3r-d.ll +++ b/test/CodeGen/Mips/msa/3r-d.ll @@ -1,7 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'd' -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> , align 16 @@ -9,8 +10,8 @@ define void @llvm_mips_div_s_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES ret void @@ -31,8 +32,8 @@ declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind define void @llvm_mips_div_s_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES ret void @@ -53,8 +54,8 @@ declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind define void @llvm_mips_div_s_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES ret void @@ -75,8 +76,8 @@ declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind define void @llvm_mips_div_s_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES ret void @@ -91,14 +92,79 @@ declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_div_s_d_test ; + +define void @div_s_b_test() nounwind { +entry: + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_s_b_ARG2 + %2 = sdiv <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES + ret void +} + +; CHECK: div_s_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: div_s.b +; CHECK: st.b +; CHECK: .size div_s_b_test + +define void @div_s_h_test() nounwind { +entry: + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_s_h_ARG2 + %2 = sdiv <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES + ret void +} + +; CHECK: div_s_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: div_s.h +; CHECK: st.h +; CHECK: .size div_s_h_test + +define void @div_s_w_test() nounwind { +entry: + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_s_w_ARG2 + %2 = sdiv <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES + ret void +} + +; CHECK: div_s_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: div_s.w +; CHECK: st.w +; CHECK: .size div_s_w_test + +define void @div_s_d_test() nounwind { +entry: + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_s_d_ARG2 + %2 = sdiv <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES + ret void +} + +; CHECK: div_s_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: div_s.d +; CHECK: st.d +; CHECK: .size div_s_d_test +; @llvm_mips_div_u_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_div_u_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_div_u_b_RES = global <16 x i8> , align 16 define void @llvm_mips_div_u_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES ret void @@ -119,8 +185,8 @@ declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind define void @llvm_mips_div_u_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES ret void @@ -141,8 +207,8 @@ declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind define void @llvm_mips_div_u_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES ret void @@ -163,8 +229,8 @@ declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind define void @llvm_mips_div_u_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES ret void @@ -179,178 +245,233 @@ declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_div_u_d_test ; -@llvm_mips_dotp_s_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_dotp_s_b_ARG2 = global <16 x i8> , align 16 -@llvm_mips_dotp_s_b_RES = global <16 x i8> , align 16 -define void @llvm_mips_dotp_s_b_test() nounwind { +define void @div_u_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_dotp_s_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_dotp_s_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.dotp.s.b(<16 x i8> %0, <16 x i8> %1) - store <16 x i8> %2, <16 x i8>* @llvm_mips_dotp_s_b_RES + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_div_u_b_ARG2 + %2 = udiv <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES ret void } -declare <16 x i8> @llvm.mips.dotp.s.b(<16 x i8>, <16 x i8>) nounwind - -; CHECK: llvm_mips_dotp_s_b_test: +; CHECK: div_u_b_test: ; CHECK: ld.b ; CHECK: ld.b -; CHECK: dotp_s.b +; CHECK: div_u.b ; CHECK: st.b -; CHECK: .size llvm_mips_dotp_s_b_test +; CHECK: .size div_u_b_test + +define void @div_u_h_test() nounwind { +entry: + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_div_u_h_ARG2 + %2 = udiv <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES + ret void +} + +; CHECK: div_u_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: div_u.h +; CHECK: st.h +; CHECK: .size div_u_h_test + +define void @div_u_w_test() nounwind { +entry: + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_div_u_w_ARG2 + %2 = udiv <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES + ret void +} + +; CHECK: div_u_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: div_u.w +; CHECK: st.w +; CHECK: .size div_u_w_test + +define void @div_u_d_test() nounwind { +entry: + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_div_u_d_ARG2 + %2 = udiv <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES + ret void +} + +; CHECK: div_u_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: div_u.d +; CHECK: st.d +; CHECK: .size div_u_d_test ; -@llvm_mips_dotp_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_dotp_s_h_ARG2 = global <8 x i16> , align 16 -@llvm_mips_dotp_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_dotp_s_h_ARG1 = global <16 x i8> , + align 16 +@llvm_mips_dotp_s_h_ARG2 = global <16 x i8> , + align 16 +@llvm_mips_dotp_s_h_RES = global <8 x i16> , + align 16 define void @llvm_mips_dotp_s_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<8 x i16> %0, <8 x i16> %1) + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_s_h_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_s_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES ret void } -declare <8 x i16> @llvm.mips.dotp.s.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dotp_s_h_test: -; CHECK: ld.h -; CHECK: ld.h +; CHECK: ld.b +; CHECK: ld.b ; CHECK: dotp_s.h ; CHECK: st.h ; CHECK: .size llvm_mips_dotp_s_h_test ; -@llvm_mips_dotp_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_dotp_s_w_ARG2 = global <4 x i32> , align 16 -@llvm_mips_dotp_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_dotp_s_w_ARG1 = global <8 x i16> , + align 16 +@llvm_mips_dotp_s_w_ARG2 = global <8 x i16> , + align 16 +@llvm_mips_dotp_s_w_RES = global <4 x i32> , + align 16 define void @llvm_mips_dotp_s_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<4 x i32> %0, <4 x i32> %1) + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_s_w_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_s_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES ret void } -declare <4 x i32> @llvm.mips.dotp.s.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dotp_s_w_test: -; CHECK: ld.w -; CHECK: ld.w +; CHECK: ld.h +; CHECK: ld.h ; CHECK: dotp_s.w ; CHECK: st.w ; CHECK: .size llvm_mips_dotp_s_w_test ; -@llvm_mips_dotp_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_dotp_s_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_dotp_s_d_ARG1 = global <4 x i32> , + align 16 +@llvm_mips_dotp_s_d_ARG2 = global <4 x i32> , + align 16 @llvm_mips_dotp_s_d_RES = global <2 x i64> , align 16 define void @llvm_mips_dotp_s_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<2 x i64> %0, <2 x i64> %1) + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_s_d_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_s_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES ret void } -declare <2 x i64> @llvm.mips.dotp.s.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dotp_s_d_test: -; CHECK: ld.d -; CHECK: ld.d +; CHECK: ld.w +; CHECK: ld.w ; CHECK: dotp_s.d ; CHECK: st.d ; CHECK: .size llvm_mips_dotp_s_d_test ; -@llvm_mips_dotp_u_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_dotp_u_b_ARG2 = global <16 x i8> , align 16 -@llvm_mips_dotp_u_b_RES = global <16 x i8> , align 16 - -define void @llvm_mips_dotp_u_b_test() nounwind { -entry: - %0 = load <16 x i8>* @llvm_mips_dotp_u_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_dotp_u_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.dotp.u.b(<16 x i8> %0, <16 x i8> %1) - store <16 x i8> %2, <16 x i8>* @llvm_mips_dotp_u_b_RES - ret void -} - -declare <16 x i8> @llvm.mips.dotp.u.b(<16 x i8>, <16 x i8>) nounwind - -; CHECK: llvm_mips_dotp_u_b_test: -; CHECK: ld.b -; CHECK: ld.b -; CHECK: dotp_u.b -; CHECK: st.b -; CHECK: .size llvm_mips_dotp_u_b_test -; -@llvm_mips_dotp_u_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_dotp_u_h_ARG2 = global <8 x i16> , align 16 -@llvm_mips_dotp_u_h_RES = global <8 x i16> , align 16 +@llvm_mips_dotp_u_h_ARG1 = global <16 x i8> , + align 16 +@llvm_mips_dotp_u_h_ARG2 = global <16 x i8> , + align 16 +@llvm_mips_dotp_u_h_RES = global <8 x i16> , + align 16 define void @llvm_mips_dotp_u_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<8 x i16> %0, <8 x i16> %1) + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_u_h_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dotp_u_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES ret void } -declare <8 x i16> @llvm.mips.dotp.u.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dotp_u_h_test: -; CHECK: ld.h -; CHECK: ld.h +; CHECK: ld.b +; CHECK: ld.b ; CHECK: dotp_u.h ; CHECK: st.h ; CHECK: .size llvm_mips_dotp_u_h_test ; -@llvm_mips_dotp_u_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_dotp_u_w_ARG2 = global <4 x i32> , align 16 -@llvm_mips_dotp_u_w_RES = global <4 x i32> , align 16 +@llvm_mips_dotp_u_w_ARG1 = global <8 x i16> , + align 16 +@llvm_mips_dotp_u_w_ARG2 = global <8 x i16> , + align 16 +@llvm_mips_dotp_u_w_RES = global <4 x i32> , + align 16 define void @llvm_mips_dotp_u_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<4 x i32> %0, <4 x i32> %1) + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_u_w_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dotp_u_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES ret void } -declare <4 x i32> @llvm.mips.dotp.u.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dotp_u_w_test: -; CHECK: ld.w -; CHECK: ld.w +; CHECK: ld.h +; CHECK: ld.h ; CHECK: dotp_u.w ; CHECK: st.w ; CHECK: .size llvm_mips_dotp_u_w_test ; -@llvm_mips_dotp_u_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_dotp_u_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_dotp_u_d_ARG1 = global <4 x i32> , + align 16 +@llvm_mips_dotp_u_d_ARG2 = global <4 x i32> , + align 16 @llvm_mips_dotp_u_d_RES = global <2 x i64> , align 16 define void @llvm_mips_dotp_u_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<2 x i64> %0, <2 x i64> %1) + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_u_d_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dotp_u_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES ret void } -declare <2 x i64> @llvm.mips.dotp.u.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dotp_u_d_test: -; CHECK: ld.d -; CHECK: ld.d +; CHECK: ld.w +; CHECK: ld.w ; CHECK: dotp_u.d ; CHECK: st.d ; CHECK: .size llvm_mips_dotp_u_d_test