X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FARM%2Freg_sequence.ll;h=507ee48cafc23f738b78552500625cf3569ac5a7;hb=9daba6f571437eb90a0fdf477f33cf0cfef9c58b;hp=6d6586e4f28397b780a64e9c291b79e1f9333953;hpb=5cf178f281b5bc52b61d4288a309a7d35ec3cc06;p=oota-llvm.git diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 6d6586e4f28..507ee48cafc 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 -regalloc=basic | FileCheck %s ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. %struct.int16x8_t = type { <8 x i16> } @@ -11,7 +11,7 @@ define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: vld1.16 ; CHECK-NOT: vmov d ; CHECK: vmovl.s16 @@ -19,10 +19,10 @@ entry: ; CHECK: vshrn.i32 ; CHECK-NOT: vmov d ; CHECK-NEXT: vst1.16 - %0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] - %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] - %2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] - %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; [#uses=1] %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] @@ -34,9 +34,11 @@ entry: %12 = sext <4 x i16> %11 to <4 x i32> ; <<4 x i32>> [#uses=1] %13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1] %14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1] - %15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> ) ; <<4 x i16>> [#uses=1] - %16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> ) ; <<4 x i16>> [#uses=1] - %17 = shufflevector <4 x i16> %15, <4 x i16> %16, <8 x i32> ; <<8 x i16>> [#uses=1] + %15 = lshr <4 x i32> %13, + %trunc_15 = trunc <4 x i32> %15 to <4 x i16> + %16 = lshr <4 x i32> %14, + %trunc_16 = trunc <4 x i32> %16 to <4 x i16> + %17 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> ; <<8 x i16>> [#uses=1] %18 = bitcast i16* %o_ptr to i8* ; [#uses=1] tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17, i32 1) ret void @@ -44,7 +46,7 @@ entry: define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: vld1.16 ; CHECK-NOT: vmov ; CHECK: vmul.i16 @@ -53,27 +55,27 @@ entry: ; CHECK-NOT: vmov ; CHECK: vst1.16 ; CHECK: vst1.16 - %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] - %1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] - %2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] - %3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] + %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %1 = load <8 x i16>, <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] + %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %3 = load <8 x i16>, <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; [#uses=1] %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] - %6 = getelementptr inbounds i16* %i_ptr, i32 8 ; [#uses=1] + %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8 ; [#uses=1] %7 = bitcast i16* %6 to i8* ; [#uses=1] %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1] %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] %11 = bitcast i16* %o_ptr to i8* ; [#uses=1] tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1) - %12 = getelementptr inbounds i16* %o_ptr, i32 8 ; [#uses=1] + %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; [#uses=1] %13 = bitcast i16* %12 to i8* ; [#uses=1] tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1) ret void } define <8 x i8> @t3(i8* %A, i8* %B) nounwind { -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 ; CHECK: vmov r @@ -92,7 +94,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { define void @t4(i32* %in, i32* %out) nounwind { entry: -; CHECK: t4: +; CHECK-LABEL: t4: ; CHECK: vld2.32 ; CHECK-NOT: vmov ; CHECK: vld2.32 @@ -100,7 +102,7 @@ entry: ; CHECK: bne %tmp1 = bitcast i32* %in to i8* ; [#uses=1] %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] - %tmp3 = getelementptr inbounds i32* %in, i32 8 ; [#uses=1] + %tmp3 = getelementptr inbounds i32, i32* %in, i32 8 ; [#uses=1] %tmp4 = bitcast i32* %tmp3 to i8* ; [#uses=1] %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp8 = bitcast i32* %out to i8* ; [#uses=1] @@ -135,7 +137,7 @@ return2: } define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { -; CHECK: t5: +; CHECK-LABEL: t5: ; CHECK: vld1.32 ; How can FileCheck match Q and D registers? We need a lisp interpreter. ; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} @@ -144,7 +146,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK-NOT: vmov ; CHECK: vadd.i16 %tmp0 = bitcast i16* %A to i8* ; [#uses=1] - %tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2] + %tmp1 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=2] %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] @@ -153,11 +155,11 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { } define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { -; CHECK: t6: +; CHECK-LABEL: t6: ; CHECK: vldr ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} - %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] + %tmp1 = load <8 x i8>, <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] @@ -167,7 +169,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { define void @t7(i32* %iptr, i32* %optr) nounwind { entry: -; CHECK: t7: +; CHECK-LABEL: t7: ; CHECK: vld2.32 ; CHECK: vst2.32 ; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, @@ -189,7 +191,7 @@ entry: ; PR7156 define arm_aapcs_vfpcc i32 @t8() nounwind { -; CHECK: t8: +; CHECK-LABEL: t8: ; CHECK: vrsqrte.f32 q8, q8 bb.nph55.bb.nph55.split_crit_edge: br label %bb3 @@ -238,12 +240,11 @@ bb14: ; preds = %bb6 ; PR7157 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { -; CHECK: t9: -; CHECK: vldr -; CHECK-NOT: vmov d{{.*}}, d16 -; CHECK: vmov.i32 d17 -; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] -; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128] +; CHECK-LABEL: t9: +; CHECK: vmov.i32 d16, #0x0 +; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] +; CHECK-NEXT: vorr d17, d16, d16 +; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 @@ -270,7 +271,7 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; PR7162 define arm_aapcs_vfpcc i32 @t10() nounwind { entry: -; CHECK: t10: +; CHECK-LABEL: t10: ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]] ; CHECK: vadd.f32 q8, q8, q8