X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FARM%2Fmulhi.ll;h=c66a804808fd845f971a3fb104d01bf6567ccc9d;hb=a5ae7c1c9fdbaaa648ae7bcf945ce714fcba91cc;hp=148f291e551d7867b0d86682f4b2f8e1080a8ce4;hpb=fce288fc9134f0f1055caf0342c023225bd5c379;p=oota-llvm.git

diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll
index 148f291e551..c66a804808f 100644
--- a/test/CodeGen/ARM/mulhi.ll
+++ b/test/CodeGen/ARM/mulhi.ll
@@ -1,9 +1,16 @@
-; RUN: llc < %s -march=arm -mattr=+v6
-; RUN: llc < %s -march=arm -mattr=+v6 | \
-; RUN:   grep smmul | count 1
-; RUN: llc < %s -march=arm | grep umull | count 1
+; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s -check-prefix=V6
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=V4
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=M3
 
-define i32 @smulhi(i32 %x, i32 %y) {
+define i32 @smulhi(i32 %x, i32 %y) nounwind {
+; V6-LABEL: smulhi:
+; V6: smmul
+
+; V4-LABEL: smulhi:
+; V4: smull
+
+; M3-LABEL: smulhi:
+; M3: smull
         %tmp = sext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = sext i32 %y to i64              ; <i64> [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
@@ -12,7 +19,15 @@ define i32 @smulhi(i32 %x, i32 %y) {
         ret i32 %tmp3.upgrd.1
 }
 
-define i32 @umulhi(i32 %x, i32 %y) {
+define i32 @umulhi(i32 %x, i32 %y) nounwind {
+; V6-LABEL: umulhi:
+; V6: umull
+
+; V4-LABEL: umulhi:
+; V4: umull
+
+; M3-LABEL: umulhi:
+; M3: umull
         %tmp = zext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = zext i32 %y to i64              ; <i64> [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
@@ -20,3 +35,20 @@ define i32 @umulhi(i32 %x, i32 %y) {
         %tmp3.upgrd.2 = trunc i64 %tmp3 to i32          ; <i32> [#uses=1]
         ret i32 %tmp3.upgrd.2
 }
+
+; rdar://r10152911
+define i32 @t3(i32 %a) nounwind {
+; V6-LABEL: t3:
+; V6: smmla
+
+; V4-LABEL: t3:
+; V4: smull
+
+; M3-LABEL: t3:
+; M3-NOT: smmla
+; M3: smull
+entry:
+  %tmp1 = mul nsw i32 %a, 3
+  %tmp2 = sdiv i32 %tmp1, 23
+  ret i32 %tmp2
+}