X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FXCore%2FXCoreRegisterInfo.cpp;h=1cfb57dc3af3073f604bb96686f113476fb3fbf3;hb=1422e1f158810323cfbe06d9242ba35c3f674921;hp=d5a96d70b5ee078ac5fb22bf30d5b97fe5fea89b;hpb=9409825b57cec078a2a90910978622073d31813d;p=oota-llvm.git

diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp
index d5a96d70b5e..1cfb57dc3af 100644
--- a/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -15,6 +15,7 @@
 #include "XCore.h"
 #include "XCoreInstrInfo.h"
 #include "XCoreMachineFunctionInfo.h"
+#include "XCoreSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -33,11 +34,13 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
+using namespace llvm;
+
+#define DEBUG_TYPE "xcore-reg-info"
+
 #define GET_REGINFO_TARGET_DESC
 #include "XCoreGenRegisterInfo.inc"
 
-using namespace llvm;
-
 XCoreRegisterInfo::XCoreRegisterInfo()
   : XCoreGenRegisterInfo(XCore::LR) {
 }
@@ -67,13 +70,15 @@ static void InsertFPImmInst(MachineBasicBlock::iterator II,
   case XCore::LDWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
           .addReg(FrameReg)
-          .addImm(Offset);
+          .addImm(Offset)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::STWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
           .addReg(FrameReg)
-          .addImm(Offset);
+          .addImm(Offset)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::LDAWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
@@ -93,22 +98,23 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II,
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc dl = MI.getDebugLoc();
-
   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
-  RS->setUsed(ScratchOffset);
+  RS->setRegUsed(ScratchOffset);
   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
 
   switch (MI.getOpcode()) {
   case XCore::LDWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
           .addReg(FrameReg)
-          .addReg(ScratchOffset, RegState::Kill);
+          .addReg(ScratchOffset, RegState::Kill)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::STWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
           .addReg(FrameReg)
-          .addReg(ScratchOffset, RegState::Kill);
+          .addReg(ScratchOffset, RegState::Kill)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::LDAWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
@@ -127,18 +133,21 @@ static void InsertSPImmInst(MachineBasicBlock::iterator II,
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc dl = MI.getDebugLoc();
   bool isU6 = isImmU6(Offset);
+
   switch (MI.getOpcode()) {
   int NewOpcode;
   case XCore::LDWFI:
     NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
     BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
-          .addImm(Offset);
+          .addImm(Offset)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::STWFI:
     NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
     BuildMI(MBB, II, dl, TII.get(NewOpcode))
           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
-          .addImm(Offset);
+          .addImm(Offset)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::LDAWFI:
     NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
@@ -162,25 +171,27 @@ static void InsertSPConstInst(MachineBasicBlock::iterator II,
   unsigned ScratchBase;
   if (OpCode==XCore::STWFI) {
     ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
-    RS->setUsed(ScratchBase);
+    RS->setRegUsed(ScratchBase);
   } else
     ScratchBase = Reg;
   BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
-  RS->setUsed(ScratchOffset);
+  RS->setRegUsed(ScratchOffset);
   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
 
   switch (OpCode) {
   case XCore::LDWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
           .addReg(ScratchBase, RegState::Kill)
-          .addReg(ScratchOffset, RegState::Kill);
+          .addReg(ScratchOffset, RegState::Kill)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::STWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
           .addReg(ScratchBase, RegState::Kill)
-          .addReg(ScratchOffset, RegState::Kill);
+          .addReg(ScratchOffset, RegState::Kill)
+          .addMemOperand(*MI.memoperands_begin());
     break;
   case XCore::LDAWFI:
     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
@@ -197,21 +208,21 @@ bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
     MF.getFunction()->needsUnwindTableEntry();
 }
 
-const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
-                                                                         const {
+const MCPhysReg *
+XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   // The callee saved registers LR & FP are explicitly handled during
   // emitPrologue & emitEpilogue and related functions.
-  static const uint16_t CalleeSavedRegs[] = {
+  static const MCPhysReg CalleeSavedRegs[] = {
     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
     XCore::R8, XCore::R9, XCore::R10,
     0
   };
-  static const uint16_t CalleeSavedRegsFP[] = {
+  static const MCPhysReg CalleeSavedRegsFP[] = {
     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
     XCore::R8, XCore::R9,
     0
   };
-  const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
+  const XCoreFrameLowering *TFI = getFrameLowering(*MF);
   if (TFI->hasFP(*MF))
     return CalleeSavedRegsFP;
   return CalleeSavedRegs;
@@ -219,7 +230,7 @@ const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
 
 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+  const XCoreFrameLowering *TFI = getFrameLowering(MF);
 
   Reserved.set(XCore::CP);
   Reserved.set(XCore::DP);
@@ -257,9 +268,9 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 
   MachineFunction &MF = *MI.getParent()->getParent();
   const XCoreInstrInfo &TII =
-          *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
+      *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
 
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+  const XCoreFrameLowering *TFI = getFrameLowering(MF);
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
   int StackSize = MF.getFrameInfo()->getStackSize();
 
@@ -313,7 +324,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 
 
 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+  const XCoreFrameLowering *TFI = getFrameLowering(MF);
 
   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
 }