X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86TargetMachine.h;h=41d51570b9ab4fa6ea0953bc46b553ae8b44f59d;hb=db1c4942760e926a6c606b924d47ec18d513b674;hp=ba73ca87d4301aeeebdad74758e16c9f4ed68581;hpb=4c1b606ecd9cb02c0ae1e468ad57d76d6d96bc26;p=oota-llvm.git diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index ba73ca87d43..41d51570b9a 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -13,104 +13,56 @@ #ifndef X86TARGETMACHINE_H #define X86TARGETMACHINE_H - -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "X86.h" -#include "X86ELFWriterInfo.h" #include "X86InstrInfo.h" -#include "X86JITInfo.h" #include "X86Subtarget.h" -#include "X86ISelLowering.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { - -class raw_ostream; - -class X86TargetMachine : public LLVMTargetMachine { - X86Subtarget Subtarget; - const TargetData DataLayout; // Calculates type size & alignment - TargetFrameInfo FrameInfo; - X86InstrInfo InstrInfo; - X86JITInfo JITInfo; - X86TargetLowering TLInfo; - X86ELFWriterInfo ELFWriterInfo; - Reloc::Model DefRelocModel; // Reloc model before it's overridden. -protected: - virtual const TargetAsmInfo *createTargetAsmInfo() const; +class StringRef; - // To avoid having target depend on the asmprinter stuff libraries, asmprinter - // set this functions to ctor pointer at startup time if they are linked in. - typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o, - X86TargetMachine &tm, - CodeGenOpt::Level OptLevel, - bool verbose); - static AsmPrinterCtorFn AsmPrinterCtor; +class X86TargetMachine final : public LLVMTargetMachine { + virtual void anchor(); + X86Subtarget Subtarget; public: - X86TargetMachine(const Module &M, const std::string &FS, bool is64Bit); + X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); - virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } - virtual X86JITInfo *getJITInfo() { return &JITInfo; } - virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual X86TargetLowering *getTargetLowering() const { - return const_cast(&TLInfo); + const DataLayout *getDataLayout() const override { + return getSubtargetImpl()->getDataLayout(); } - virtual const X86RegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); + const X86InstrInfo *getInstrInfo() const override { + return getSubtargetImpl()->getInstrInfo(); } - virtual const TargetData *getTargetData() const { return &DataLayout; } - virtual const X86ELFWriterInfo *getELFWriterInfo() const { - return Subtarget.isTargetELF() ? &ELFWriterInfo : 0; + const TargetFrameLowering *getFrameLowering() const override { + return getSubtargetImpl()->getFrameLowering(); } - - static unsigned getModuleMatchQuality(const Module &M); - static unsigned getJITMatchQuality(); - - static void registerAsmPrinter(AsmPrinterCtorFn F) { - AsmPrinterCtor = F; + X86JITInfo *getJITInfo() override { return Subtarget.getJITInfo(); } + const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } + const X86TargetLowering *getTargetLowering() const override { + return getSubtargetImpl()->getTargetLowering(); + } + const X86SelectionDAGInfo *getSelectionDAGInfo() const override { + return getSubtargetImpl()->getSelectionDAGInfo(); + } + const X86RegisterInfo *getRegisterInfo() const override { + return &getInstrInfo()->getRegisterInfo(); + } + const InstrItineraryData *getInstrItineraryData() const override { + return &getSubtargetImpl()->getInstrItineraryData(); } - // Set up the pass pipeline. - virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addAssemblyEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - bool Verbose, raw_ostream &Out); - virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE); - virtual bool addSimpleCodeEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE); -}; + /// \brief Register X86 analysis passes with a pass manager. + void addAnalysisPasses(PassManagerBase &PM) override; -/// X86_32TargetMachine - X86 32-bit target machine. -/// -class X86_32TargetMachine : public X86TargetMachine { -public: - X86_32TargetMachine(const Module &M, const std::string &FS); - - static unsigned getJITMatchQuality(); - static unsigned getModuleMatchQuality(const Module &M); -}; + // Set up the pass pipeline. + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; -/// X86_64TargetMachine - X86 64-bit target machine. -/// -class X86_64TargetMachine : public X86TargetMachine { -public: - X86_64TargetMachine(const Module &M, const std::string &FS); - - static unsigned getJITMatchQuality(); - static unsigned getModuleMatchQuality(const Module &M); + bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override; }; } // End llvm namespace