X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86TargetMachine.h;h=41d51570b9ab4fa6ea0953bc46b553ae8b44f59d;hb=db1c4942760e926a6c606b924d47ec18d513b674;hp=70b111c38bf3af57c0b5f9531b775b9e67025a41;hpb=0431c96cec9576611f06c513d6adcab0f950c18c;p=oota-llvm.git diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 70b111c38bf..41d51570b9a 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -13,45 +13,58 @@ #ifndef X86TARGETMACHINE_H #define X86TARGETMACHINE_H - -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/PassManager.h" #include "X86InstrInfo.h" -#include "X86JITInfo.h" +#include "X86Subtarget.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { -class IntrinsicLowering; -class X86TargetMachine : public TargetMachine { - X86InstrInfo InstrInfo; - TargetFrameInfo FrameInfo; - X86JITInfo JITInfo; +class StringRef; + +class X86TargetMachine final : public LLVMTargetMachine { + virtual void anchor(); + X86Subtarget Subtarget; + public: - X86TargetMachine(const Module &M, IntrinsicLowering *IL); + X86TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); - virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } - virtual TargetJITInfo *getJITInfo() { return &JITInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); + const DataLayout *getDataLayout() const override { + return getSubtargetImpl()->getDataLayout(); + } + const X86InstrInfo *getInstrInfo() const override { + return getSubtargetImpl()->getInstrInfo(); + } + const TargetFrameLowering *getFrameLowering() const override { + return getSubtargetImpl()->getFrameLowering(); + } + X86JITInfo *getJITInfo() override { return Subtarget.getJITInfo(); } + const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } + const X86TargetLowering *getTargetLowering() const override { + return getSubtargetImpl()->getTargetLowering(); + } + const X86SelectionDAGInfo *getSelectionDAGInfo() const override { + return getSubtargetImpl()->getSelectionDAGInfo(); + } + const X86RegisterInfo *getRegisterInfo() const override { + return &getInstrInfo()->getRegisterInfo(); + } + const InstrItineraryData *getInstrItineraryData() const override { + return &getSubtargetImpl()->getInstrItineraryData(); } - /// addPassesToEmitMachineCode - Add passes to the specified pass manager to - /// get machine code emitted. This uses a MachineCodeEmitter object to handle - /// actually outputting the machine code and resolving things like the address - /// of functions. This method should returns true if machine code emission is - /// not supported. - /// - virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM, - MachineCodeEmitter &MCE); + /// \brief Register X86 analysis passes with a pass manager. + void addAnalysisPasses(PassManagerBase &PM) override; - virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, - CodeGenFileType FileType); + // Set up the pass pipeline. + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - static unsigned getModuleMatchQuality(const Module &M); - static unsigned getJITMatchQuality(); + bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override; }; + } // End llvm namespace #endif