X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86TargetMachine.cpp;h=d094d900665f65202994433d2ef7cd4e7eb73d31;hb=b576c94c15af9a440f69d9d03c2afead7971118c;hp=4113d0e6dc8948772d2389fc5dc441c35b3cc339;hpb=155e68feea21534d69be3cdbcc16991398b7664a;p=oota-llvm.git

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 4113d0e6dc8..d094d900665 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -1,11 +1,19 @@
 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
 // 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+// 
 // This file defines the X86 specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86TargetMachine.h"
 #include "X86.h"
+#include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/Target/TargetMachineImpls.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -13,43 +21,99 @@
 #include "llvm/Transforms/Scalar.h"
 #include "Support/CommandLine.h"
 #include "Support/Statistic.h"
-#include <iostream>
 
 namespace {
-  cl::opt<bool> NoLocalRA("disable-local-ra",
-                          cl::desc("Use Simple RA instead of Local RegAlloc"));
   cl::opt<bool> PrintCode("print-machineinstrs",
 			  cl::desc("Print generated machine code"));
+  cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
+                        cl::desc("Use the 'simple' X86 instruction selector"));
 }
 
 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
 // that implements the X86 backend.
 //
-TargetMachine *allocateX86TargetMachine(unsigned Configuration) {
-  return new X86TargetMachine(Configuration);
+TargetMachine *allocateX86TargetMachine(const Module &M) {
+  return new X86TargetMachine(M);
 }
 
 
 /// X86TargetMachine ctor - Create an ILP32 architecture model
 ///
-X86TargetMachine::X86TargetMachine(unsigned Config)
-  : TargetMachine("X86", 
-		  (Config & TM::EndianMask) == TM::LittleEndian,
-		  1, 4, 
-		  (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
-		  (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4),
-  FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
+X86TargetMachine::X86TargetMachine(const Module &M)
+  : TargetMachine("X86", true, 4, 4, 4, 4, 4),
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4) {
+}
+
+
+// addPassesToEmitAssembly - We currently use all of the same passes as the JIT
+// does to emit statically compiled machine code.
+bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
+					       std::ostream &Out) {
+  // FIXME: Implement the switch instruction in the instruction selector!
+  PM.add(createLowerSwitchPass());
+
+  // FIXME: Implement the invoke/unwind instructions!
+  PM.add(createLowerInvokePass());
+
+  // FIXME: The code generator does not properly handle functions with
+  // unreachable basic blocks.
+  PM.add(createCFGSimplificationPass());
+
+  if (NoPatternISel)
+    PM.add(createX86SimpleInstructionSelector(*this));
+  else
+    PM.add(createX86PatternInstructionSelector(*this));
+
+  // TODO: optional optimizations go here
+
+  // FIXME: Add SSA based peephole optimizer here.
+
+  // Print the instruction selected machine code...
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  // Perform register allocation to convert to a concrete x86 representation
+  PM.add(createRegisterAllocator());
+
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  PM.add(createX86FloatingPointStackifierPass());
+
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
+
+  // Insert prolog/epilog code.  Eliminate abstract frame index references...
+  PM.add(createPrologEpilogCodeInserter());
+
+  PM.add(createX86PeepholeOptimizerPass());
+
+  if (PrintCode)  // Print the register-allocated code
+    PM.add(createX86CodePrinterPass(std::cerr, *this));
+
+  PM.add(createX86CodePrinterPass(Out, *this));
+  return false; // success!
 }
 
 /// addPassesToJITCompile - Add passes to the specified pass manager to
 /// implement a fast dynamic compiler for this target.  Return true if this is
 /// not supported for this target.
 ///
-bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
+bool X86TargetMachine::addPassesToJITCompile(FunctionPassManager &PM) {
   // FIXME: Implement the switch instruction in the instruction selector!
   PM.add(createLowerSwitchPass());
 
-  PM.add(createSimpleX86InstructionSelector(*this));
+  // FIXME: Implement the invoke/unwind instructions!
+  PM.add(createLowerInvokePass());
+
+  // FIXME: The code generator does not properly handle functions with
+  // unreachable basic blocks.
+  PM.add(createCFGSimplificationPass());
+
+  if (NoPatternISel)
+    PM.add(createX86SimpleInstructionSelector(*this));
+  else
+    PM.add(createX86PatternInstructionSelector(*this));
 
   // TODO: optional optimizations go here
 
@@ -60,10 +124,7 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
     PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
-  if (NoLocalRA)
-    PM.add(createSimpleRegisterAllocator());
-  else
-    PM.add(createLocalRegisterAllocator());
+  PM.add(createRegisterAllocator());
 
   if (PrintCode)
     PM.add(createMachineFunctionPrinterPass());
@@ -79,8 +140,16 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
   PM.add(createX86PeepholeOptimizerPass());
 
   if (PrintCode)  // Print the register-allocated code
-    PM.add(createX86CodePrinterPass(std::cerr));
-
+    PM.add(createX86CodePrinterPass(std::cerr, *this));
   return false; // success!
 }
 
+void X86TargetMachine::replaceMachineCodeForFunction (void *Old, void *New) {
+  // FIXME: This code could perhaps live in a more appropriate place.
+  char *OldByte = (char *) Old;
+  *OldByte++ = 0xE9;                // Emit JMP opcode.
+  int32_t *OldWord = (int32_t *) OldByte;
+  int32_t NewAddr = (int32_t) New;
+  int32_t OldAddr = (int32_t) OldWord;
+  *OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code.
+}