X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86TargetMachine.cpp;h=08753e70e8c9bc07fee23b6c2ba48a629ed30b71;hb=8490322fa9d4c3359015510e772e231273476739;hp=d92ae498cf0cde540cf6c5163d618b2dc0b174db;hpb=317848f4a11f7fe55afdd6d90ded8444069b56fb;p=oota-llvm.git diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index d92ae498cf0..08753e70e8c 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,9 +18,9 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetMachineRegistry.h" -#include "llvm/Transforms/Scalar.h" using namespace llvm; /// X86TargetMachineModule - Note that this is used on hosts that cannot link @@ -30,16 +30,32 @@ using namespace llvm; extern "C" int X86TargetMachineModule; int X86TargetMachineModule = 0; -namespace { - // Register the target. - RegisterTarget - X("x86", " 32-bit X86: Pentium-Pro and above"); - RegisterTarget - Y("x86-64", " 64-bit X86: EM64T and AMD64"); -} +// Register the target. +static RegisterTarget +X("x86", " 32-bit X86: Pentium-Pro and above"); +static RegisterTarget +Y("x86-64", " 64-bit X86: EM64T and AMD64"); + +// No assembler printer by default +X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0; const TargetAsmInfo *X86TargetMachine::createTargetAsmInfo() const { - return new X86TargetAsmInfo(*this); + if (Subtarget.isFlavorIntel()) + return new X86WinTargetAsmInfo(*this); + else + switch (Subtarget.TargetType) { + case X86Subtarget::isDarwin: + return new X86DarwinTargetAsmInfo(*this); + case X86Subtarget::isELF: + return new X86ELFTargetAsmInfo(*this); + case X86Subtarget::isMingw: + case X86Subtarget::isCygwin: + return new X86COFFTargetAsmInfo(*this); + case X86Subtarget::isWindows: + return new X86WinTargetAsmInfo(*this); + default: + return new X86GenericTargetAsmInfo(*this); + } } unsigned X86_32TargetMachine::getJITMatchQuality() { @@ -50,7 +66,7 @@ unsigned X86_32TargetMachine::getJITMatchQuality() { } unsigned X86_64TargetMachine::getJITMatchQuality() { -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(_M_AMD64) return 10; #endif return 0; @@ -62,6 +78,8 @@ unsigned X86_32TargetMachine::getModuleMatchQuality(const Module &M) { if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' && TT[4] == '-' && TT[1] - '3' < 6) return 20; + // If the target triple is something non-X86, we don't match. + if (!TT.empty()) return 0; if (M.getEndianness() == Module::LittleEndian && M.getPointerSize() == Module::Pointer32) @@ -85,6 +103,9 @@ unsigned X86_64TargetMachine::getModuleMatchQuality(const Module &M) { TT[3] == '6' && TT[4] == '4' && TT[5] == '-') return 20; + // If the target triple is something non-X86-64, we don't match. + if (!TT.empty()) return 0; + if (M.getEndianness() == Module::LittleEndian && M.getPointerSize() == Module::Pointer64) return 10; // Weak match @@ -106,19 +127,22 @@ X86_64TargetMachine::X86_64TargetMachine(const Module &M, const std::string &FS) /// X86TargetMachine ctor - Create an ILP32 architecture model /// -X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, bool is64Bit) +X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, + bool is64Bit) : Subtarget(M, FS, is64Bit), - DataLayout(Subtarget.is64Bit() ? - std::string("e-p:64:64-d:32-l:32") : - std::string("e-p:32:32-d:32-l:32")), + DataLayout(Subtarget.getDataLayout()), FrameInfo(TargetFrameInfo::StackGrowsDown, Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4), InstrInfo(*this), JITInfo(*this), TLInfo(*this) { - if (getRelocationModel() == Reloc::Default) - if (Subtarget.isTargetDarwin() || Subtarget.isTargetCygMing()) + DefRelocModel = getRelocationModel(); + // FIXME: Correctly select PIC model for Win64 stuff + if (getRelocationModel() == Reloc::Default) { + if (Subtarget.isTargetDarwin() || + (Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64())) setRelocationModel(Reloc::DynamicNoPIC); else setRelocationModel(Reloc::Static); + } if (Subtarget.is64Bit()) { // No DynamicNoPIC support under X86-64. if (getRelocationModel() == Reloc::DynamicNoPIC) @@ -127,46 +151,88 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, bool if (getCodeModel() == CodeModel::Default) setCodeModel(CodeModel::Small); } + + if (Subtarget.isTargetCygMing()) + Subtarget.setPICStyle(PICStyle::WinPIC); + else if (Subtarget.isTargetDarwin()) { + if (Subtarget.is64Bit()) + Subtarget.setPICStyle(PICStyle::RIPRel); + else + Subtarget.setPICStyle(PICStyle::Stub); + } else if (Subtarget.isTargetELF()) { + if (Subtarget.is64Bit()) + Subtarget.setPICStyle(PICStyle::RIPRel); + else + Subtarget.setPICStyle(PICStyle::GOT); + } } //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool X86TargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) { +bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) { // Install an instruction selector. PM.add(createX86ISelDag(*this, Fast)); return false; } -bool X86TargetMachine::addPostRegAlloc(FunctionPassManager &PM, bool Fast) { +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) { + // Calculate and set max stack object alignment early, so we can decide + // whether we will need stack realignment (and thus FP). + PM.add(createX86MaxStackAlignmentCalculatorPass()); + return false; // -print-machineinstr shouldn't print after this. +} + +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) { PM.add(createX86FloatingPointStackifierPass()); return true; // -print-machineinstr should print after this. } -bool X86TargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast, - std::ostream &Out) { - PM.add(createX86CodePrinterPass(Out, *this)); +bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, + raw_ostream &Out) { + assert(AsmPrinterCtor && "AsmPrinter was not linked in"); + if (AsmPrinterCtor) + PM.add(AsmPrinterCtor(Out, *this)); return false; } -bool X86TargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast, - std::ostream &Out) { - if (Subtarget.isTargetELF()) { - addX86ELFObjectWriterPass(PM, Out, *this); - return false; +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast, + bool DumpAsm, MachineCodeEmitter &MCE) { + // FIXME: Move this to TargetJITInfo! + // On Darwin, do not override 64-bit setting made in X86TargetMachine(). + if (DefRelocModel == Reloc::Default && + (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) + setRelocationModel(Reloc::Static); + + // 64-bit JIT places everything in the same buffer except external functions. + // On Darwin, use small code model but hack the call instruction for + // externals. Elsewhere, do not assume globals are in the lower 4G. + if (Subtarget.is64Bit()) { + if (Subtarget.isTargetDarwin()) + setCodeModel(CodeModel::Small); + else + setCodeModel(CodeModel::Large); + } + + PM.add(createX86CodeEmitterPass(*this, MCE)); + if (DumpAsm) { + assert(AsmPrinterCtor && "AsmPrinter was not linked in"); + if (AsmPrinterCtor) + PM.add(AsmPrinterCtor(errs(), *this)); } - return true; -} -bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast, - MachineCodeEmitter &MCE) { - // FIXME: Move this to TargetJITInfo! - setRelocationModel(Reloc::Static); - // JIT cannot ensure globals are placed in the lower 4G of address. - if (Subtarget.is64Bit()) - setCodeModel(CodeModel::Large); + return false; +} +bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast, + bool DumpAsm, MachineCodeEmitter &MCE) { PM.add(createX86CodeEmitterPass(*this, MCE)); + if (DumpAsm) { + assert(AsmPrinterCtor && "AsmPrinter was not linked in"); + if (AsmPrinterCtor) + PM.add(AsmPrinterCtor(errs(), *this)); + } + return false; }