X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86SchedHaswell.td;h=677e82459766d510a265a966c8fd0bb83a0bab2d;hb=d7ef3dae862793fd92c9eadb587bc108ac122d56;hp=99903006f20902beb44d58f7d7cf47c31918b64d;hpb=487ecab8d41e70700ca27895127b99f955e31fd0;p=oota-llvm.git diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index 99903006f20..677e8245976 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -53,12 +53,12 @@ def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; -def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; +def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; -def HWPort56: ProcResGroup<[HWPort5, HWPort6]>; +def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; -def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>; +def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; // 60 Entry Unified Scheduler @@ -129,6 +129,7 @@ defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; // 10-14 cycles. defm : HWWriteResPair; +defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; @@ -269,35 +270,20 @@ def : WriteRes; //================ Exceptions ================// //-- Specific Scheduling Models --// -def WriteP0 : SchedWriteRes<[HWPort0]>; -def WriteP1 : SchedWriteRes<[HWPort1]>; -def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { - let NumMicroOps = 2; -} -def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> { - let Latency = 3; -} -def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> { - let Latency = 7; -} -def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> { - let Latency = 2; - let ResourceCycles = [2]; -} -def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> { - let Latency = 6; - let ResourceCycles = [2, 1]; -} +// Starting with P0. +def WriteP0 : SchedWriteRes<[HWPort0]>; -def Write5P0156 : SchedWriteRes<[HWPort0156]> { - let NumMicroOps = 5; - let ResourceCycles = [5]; +def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1, 1]; } -def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> { - let Latency = 1; - let ResourceCycles = [2, 1]; +def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1, 1, 1]; } def WriteP01 : SchedWriteRes<[HWPort01]>; @@ -322,27 +308,33 @@ def Write2P06 : SchedWriteRes<[HWPort06]> { let ResourceCycles = [2]; } -def Write2P1 : SchedWriteRes<[HWPort1]> { +def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} + +def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { let NumMicroOps = 2; - let ResourceCycles = [2]; } -def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { + +def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { let NumMicroOps = 3; let ResourceCycles = [2, 1]; } -def WriteP15 : SchedWriteRes<[HWPort15]>; -def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> { - let Latency = 4; -} -def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> { +def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> { let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [3]; + let ResourceCycles = [2]; +} +def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> { + let Latency = 6; + let ResourceCycles = [2, 1]; } -def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { - let NumMicroOps = 2; +def Write5P0156 : SchedWriteRes<[HWPort0156]> { + let NumMicroOps = 5; + let ResourceCycles = [5]; } def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { @@ -355,33 +347,35 @@ def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { let ResourceCycles = [2, 2, 1]; } -def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; -} - def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { let Latency = 1; let ResourceCycles = [3, 2, 1]; } -def WriteP5 : SchedWriteRes<[HWPort5]>; -def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> { - let Latency = 5; +// Starting with P1. +def WriteP1 : SchedWriteRes<[HWPort1]>; + +def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +} +def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> { + let Latency = 3; +} +def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> { + let Latency = 7; } -def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> { - let Latency = 4; +def Write2P1 : SchedWriteRes<[HWPort1]> { let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [2]; } - -def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> { - let Latency = 8; +def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; + let ResourceCycles = [2, 1]; +} +def WriteP15 : SchedWriteRes<[HWPort15]>; +def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> { + let Latency = 4; } def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> { @@ -408,6 +402,20 @@ def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { let ResourceCycles = [1, 1, 1]; } +// Starting with P2. +def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> { + let Latency = 1; + let ResourceCycles = [2, 1]; +} + +// Starting with P5. +def WriteP5 : SchedWriteRes<[HWPort5]>; +def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1, 1]; +} + // Notation: // - r: register. // - mm: 64 bit mmx register. @@ -1887,7 +1895,7 @@ def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>; // x,m / v,v,m. def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> { - let Latency = 4; + let Latency = 9; let NumMicroOps = 2; let ResourceCycles = [1, 1]; } @@ -2006,7 +2014,7 @@ def : InstRW<[WriteFMADDr], // 3p forms. "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?", // 3s forms. - "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)r", + "VF(N?)M(ADD|SUB)S(S|D)(r132|r231|r213)r", // 4s/4s_int forms. "VF(N?)M(ADD|SUB)S(S|D)4rr(_REV|_Int)?", // 4p forms. @@ -2023,7 +2031,7 @@ def : InstRW<[WriteFMADDm], // 3p forms. "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?", // 3s forms. - "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)m", + "VF(N?)M(ADD|SUB)S(S|D)(r132|r231|r213)m", // 4s/4s_int forms. "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)(_Int)?", // 4p forms. @@ -2097,4 +2105,43 @@ def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { } def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>; +//-- Logic instructions --// + +// AND, ANDN, OR, XOR PS/PD. +// x,x / v,v,v. +def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>; +// x,m / v,v,m. +def : InstRW<[WriteP5Ld, ReadAfterLd], + (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>; + +//-- Other instructions --// + +// VZEROUPPER. +def WriteVZEROUPPER : SchedWriteRes<[]> { + let NumMicroOps = 4; +} +def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>; + +// VZEROALL. +def WriteVZEROALL : SchedWriteRes<[]> { + let NumMicroOps = 12; +} +def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>; + +// LDMXCSR. +def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [1, 1, 1]; +} +def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>; + +// STMXCSR. +def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1, 1, 1, 1]; +} +def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>; + } // SchedModel