X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrInfo.h;h=600e3922a71e161b6714b9c43480836c01035762;hb=35f15e54a91652738d7d3fd858e0389001d3d806;hp=f33620641e88ce20b93eb1db82f3b3e263e61245;hpb=e943c15621035fa7fbeda7b4922d06a8c2b05b2d;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index f33620641e8..600e3922a71 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -1,4 +1,4 @@ -//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// +//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -14,34 +14,19 @@ #ifndef X86INSTRUCTIONINFO_H #define X86INSTRUCTIONINFO_H -#include "llvm/Target/TargetInstrInfo.h" #include "X86.h" #include "X86RegisterInfo.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/Target/TargetInstrInfo.h" + +#define GET_INSTRINFO_HEADER +#include "X86GenInstrInfo.inc" namespace llvm { class X86RegisterInfo; class X86TargetMachine; namespace X86 { - // Enums for memory operand decoding. Each memory operand is represented with - // a 5 operand sequence in the form: - // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] - // These enums help decode this. - enum { - AddrBaseReg = 0, - AddrScaleAmt = 1, - AddrIndexReg = 2, - AddrDisp = 3, - - /// AddrSegmentReg - The operand # of the segment in the memory operand. - AddrSegmentReg = 4, - - /// AddrNumOperands - Total number of operands in a memory reference. - AddrNumOperands = 5 - }; - - // X86 specific condition code. These correspond to X86_*_COND in // X86InstrInfo.td. They must be kept in synch. enum CondCode { @@ -72,140 +57,18 @@ namespace X86 { COND_INVALID }; - + // Turn condition code into conditional branch opcode. unsigned GetCondBranchFromCond(CondCode CC); - + + // Turn CMov opcode into condition code. + CondCode getCondFromCMovOpc(unsigned Opc); + /// GetOppositeBranchCondition - Return the inverse of the specified cond, /// e.g. turning COND_E to COND_NE. CondCode GetOppositeBranchCondition(X86::CondCode CC); +} // end namespace X86; -} - -/// X86II - This namespace holds all of the target specific flags that -/// instruction info tracks. -/// -namespace X86II { - /// Target Operand Flag enum. - enum TOF { - //===------------------------------------------------------------------===// - // X86 Specific MachineOperand flags. - - MO_NO_FLAG, - - /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a - /// relocation of: - /// SYMBOL_LABEL + [. - PICBASELABEL] - MO_GOT_ABSOLUTE_ADDRESS, - - /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the - /// immediate should get the value of the symbol minus the PIC base label: - /// SYMBOL_LABEL - PICBASELABEL - MO_PIC_BASE_OFFSET, - - /// MO_GOT - On a symbol operand this indicates that the immediate is the - /// offset to the GOT entry for the symbol name from the base of the GOT. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOT - MO_GOT, - - /// MO_GOTOFF - On a symbol operand this indicates that the immediate is - /// the offset to the location of the symbol name from the base of the GOT. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOTOFF - MO_GOTOFF, - - /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is - /// offset to the GOT entry for the symbol name from the current code - /// location. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @GOTPCREL - MO_GOTPCREL, - - /// MO_PLT - On a symbol operand this indicates that the immediate is - /// offset to the PLT entry of symbol name from the current code location. - /// - /// See the X86-64 ELF ABI supplement for more details. - /// SYMBOL_LABEL @PLT - MO_PLT, - - /// MO_TLSGD - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @TLSGD - MO_TLSGD, - - /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @GOTTPOFF - MO_GOTTPOFF, - - /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @INDNTPOFF - MO_INDNTPOFF, - - /// MO_TPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @TPOFF - MO_TPOFF, - - /// MO_NTPOFF - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// See 'ELF Handling for Thread-Local Storage' for more details. - /// SYMBOL_LABEL @NTPOFF - MO_NTPOFF, - - /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "__imp_FOO" symbol. This is used for - /// dllimport linkage on windows. - MO_DLLIMPORT, - - /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "FOO$stub" symbol. This is used for calls - /// and jumps to external functions on Tiger and before. - MO_DARWIN_STUB, - - /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the - /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a - /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. - MO_DARWIN_NONLAZY, - - /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates - /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is - /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. - MO_DARWIN_NONLAZY_PIC_BASE, - - /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this - /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", - /// which is a PIC-base-relative reference to a hidden dyld lazy pointer - /// stub. - MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, - - /// MO_TLVP - On a symbol operand this indicates that the immediate is - /// some TLS offset. - /// - /// This is the TLS offset for the Darwin TLS mechanism. - MO_TLVP, - - /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate - /// is some TLS offset from the picbase. - /// - /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. - MO_TLVP_PIC_BASE - }; -} /// isGlobalStubReference - Return true if the specified TargetFlag operand is /// a reference to a stub for a global, not the global itself. @@ -239,334 +102,6 @@ inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { return false; } } - -/// X86II - This namespace holds all of the target specific flags that -/// instruction info tracks. -/// -namespace X86II { - enum { - //===------------------------------------------------------------------===// - // Instruction encodings. These are the standard/most common forms for X86 - // instructions. - // - - // PseudoFrm - This represents an instruction that is a pseudo instruction - // or one that has not been implemented yet. It is illegal to code generate - // it, but tolerated for intermediate implementation stages. - Pseudo = 0, - - /// Raw - This form is for instructions that don't have any operands, so - /// they are just a fixed opcode value, like 'leave'. - RawFrm = 1, - - /// AddRegFrm - This form is used for instructions like 'push r32' that have - /// their one register operand added to their opcode. - AddRegFrm = 2, - - /// MRMDestReg - This form is used for instructions that use the Mod/RM byte - /// to specify a destination, which in this case is a register. - /// - MRMDestReg = 3, - - /// MRMDestMem - This form is used for instructions that use the Mod/RM byte - /// to specify a destination, which in this case is memory. - /// - MRMDestMem = 4, - - /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte - /// to specify a source, which in this case is a register. - /// - MRMSrcReg = 5, - - /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte - /// to specify a source, which in this case is memory. - /// - MRMSrcMem = 6, - - /// MRM[0-7][rm] - These forms are used to represent instructions that use - /// a Mod/RM byte, and use the middle field to hold extended opcode - /// information. In the intel manual these are represented as /0, /1, ... - /// - - // First, instructions that operate on a register r/m operand... - MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 - MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 - - // Next, instructions that operate on a memory r/m operand... - MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 - MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 - - // MRMInitReg - This form is used for instructions whose source and - // destinations are the same register. - MRMInitReg = 32, - - //// MRM_C1 - A mod/rm byte of exactly 0xC1. - MRM_C1 = 33, - MRM_C2 = 34, - MRM_C3 = 35, - MRM_C4 = 36, - MRM_C8 = 37, - MRM_C9 = 38, - MRM_E8 = 39, - MRM_F0 = 40, - MRM_F8 = 41, - MRM_F9 = 42, - - /// RawFrmImm16 - This is used for CALL FAR instructions, which have two - /// immediates, the first of which is a 16 or 32-bit immediate (specified by - /// the imm encoding) and the second is a 16-bit fixed value. In the AMD - /// manual, this operand is described as pntr16:32 and pntr16:16 - RawFrmImm16 = 43, - - FormMask = 63, - - //===------------------------------------------------------------------===// - // Actual flags... - - // OpSize - Set if this instruction requires an operand size prefix (0x66), - // which most often indicates that the instruction operates on 16 bit data - // instead of 32 bit data. - OpSize = 1 << 6, - - // AsSize - Set if this instruction requires an operand size prefix (0x67), - // which most often indicates that the instruction address 16 bit address - // instead of 32 bit address (or 32 bit address in 64 bit mode). - AdSize = 1 << 7, - - //===------------------------------------------------------------------===// - // Op0Mask - There are several prefix bytes that are used to form two byte - // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is - // used to obtain the setting of this field. If no bits in this field is - // set, there is no prefix byte for obtaining a multibyte opcode. - // - Op0Shift = 8, - Op0Mask = 0xF << Op0Shift, - - // TB - TwoByte - Set if this instruction has a two byte opcode, which - // starts with a 0x0F byte before the real opcode. - TB = 1 << Op0Shift, - - // REP - The 0xF3 prefix byte indicating repetition of the following - // instruction. - REP = 2 << Op0Shift, - - // D8-DF - These escape opcodes are used by the floating point unit. These - // values must remain sequential. - D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, - DA = 5 << Op0Shift, DB = 6 << Op0Shift, - DC = 7 << Op0Shift, DD = 8 << Op0Shift, - DE = 9 << Op0Shift, DF = 10 << Op0Shift, - - // XS, XD - These prefix codes are for single and double precision scalar - // floating point operations performed in the SSE registers. - XD = 11 << Op0Shift, XS = 12 << Op0Shift, - - // T8, TA - Prefix after the 0x0F prefix. - T8 = 13 << Op0Shift, TA = 14 << Op0Shift, - - // TF - Prefix before and after 0x0F - TF = 15 << Op0Shift, - - //===------------------------------------------------------------------===// - // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. - // They are used to specify GPRs and SSE registers, 64-bit operand size, - // etc. We only cares about REX.W and REX.R bits and only the former is - // statically determined. - // - REXShift = 12, - REX_W = 1 << REXShift, - - //===------------------------------------------------------------------===// - // This three-bit field describes the size of an immediate operand. Zero is - // unused so that we can tell if we forgot to set a value. - ImmShift = 13, - ImmMask = 7 << ImmShift, - Imm8 = 1 << ImmShift, - Imm8PCRel = 2 << ImmShift, - Imm16 = 3 << ImmShift, - Imm16PCRel = 4 << ImmShift, - Imm32 = 5 << ImmShift, - Imm32PCRel = 6 << ImmShift, - Imm64 = 7 << ImmShift, - - //===------------------------------------------------------------------===// - // FP Instruction Classification... Zero is non-fp instruction. - - // FPTypeMask - Mask for all of the FP types... - FPTypeShift = 16, - FPTypeMask = 7 << FPTypeShift, - - // NotFP - The default, set for instructions that do not use FP registers. - NotFP = 0 << FPTypeShift, - - // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 - ZeroArgFP = 1 << FPTypeShift, - - // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst - OneArgFP = 2 << FPTypeShift, - - // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a - // result back to ST(0). For example, fcos, fsqrt, etc. - // - OneArgFPRW = 3 << FPTypeShift, - - // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an - // explicit argument, storing the result to either ST(0) or the implicit - // argument. For example: fadd, fsub, fmul, etc... - TwoArgFP = 4 << FPTypeShift, - - // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an - // explicit argument, but have no destination. Example: fucom, fucomi, ... - CompareFP = 5 << FPTypeShift, - - // CondMovFP - "2 operand" floating point conditional move instructions. - CondMovFP = 6 << FPTypeShift, - - // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. - SpecialFP = 7 << FPTypeShift, - - // Lock prefix - LOCKShift = 19, - LOCK = 1 << LOCKShift, - - // Segment override prefixes. Currently we just need ability to address - // stuff in gs and fs segments. - SegOvrShift = 20, - SegOvrMask = 3 << SegOvrShift, - FS = 1 << SegOvrShift, - GS = 2 << SegOvrShift, - - // Execution domain for SSE instructions in bits 22, 23. - // 0 in bits 22-23 means normal, non-SSE instruction. - SSEDomainShift = 22, - - OpcodeShift = 24, - OpcodeMask = 0xFF << OpcodeShift, - - //===------------------------------------------------------------------===// - // VEX - The opcode prefix used by AVX instructions - VEX = 1U << 0, - - // VEX_W - Has a opcode specific functionality, but is used in the same - // way as REX_W is for regular SSE instructions. - VEX_W = 1U << 1, - - // VEX_4V - Used to specify an additional AVX/SSE register. Several 2 - // address instructions in SSE are represented as 3 address ones in AVX - // and the additional register is encoded in VEX_VVVV prefix. - VEX_4V = 1U << 2, - - // VEX_I8IMM - Specifies that the last register used in a AVX instruction, - // must be encoded in the i8 immediate field. This usually happens in - // instructions with 4 operands. - VEX_I8IMM = 1U << 3, - - // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current - // instruction uses 256-bit wide registers. This is usually auto detected if - // a VR256 register is used, but some AVX instructions also have this field - // marked when using a f256 memory references. - VEX_L = 1U << 4 - }; - - // getBaseOpcodeFor - This function returns the "base" X86 opcode for the - // specified machine instruction. - // - static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { - return TSFlags >> X86II::OpcodeShift; - } - - static inline bool hasImm(uint64_t TSFlags) { - return (TSFlags & X86II::ImmMask) != 0; - } - - /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field - /// of the specified instruction. - static inline unsigned getSizeOfImm(uint64_t TSFlags) { - switch (TSFlags & X86II::ImmMask) { - default: assert(0 && "Unknown immediate size"); - case X86II::Imm8: - case X86II::Imm8PCRel: return 1; - case X86II::Imm16: - case X86II::Imm16PCRel: return 2; - case X86II::Imm32: - case X86II::Imm32PCRel: return 4; - case X86II::Imm64: return 8; - } - } - - /// isImmPCRel - Return true if the immediate of the specified instruction's - /// TSFlags indicates that it is pc relative. - static inline unsigned isImmPCRel(uint64_t TSFlags) { - switch (TSFlags & X86II::ImmMask) { - default: assert(0 && "Unknown immediate size"); - case X86II::Imm8PCRel: - case X86II::Imm16PCRel: - case X86II::Imm32PCRel: - return true; - case X86II::Imm8: - case X86II::Imm16: - case X86II::Imm32: - case X86II::Imm64: - return false; - } - } - - /// getMemoryOperandNo - The function returns the MCInst operand # for the - /// first field of the memory operand. If the instruction doesn't have a - /// memory operand, this returns -1. - /// - /// Note that this ignores tied operands. If there is a tied register which - /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only - /// counted as one operand. - /// - static inline int getMemoryOperandNo(uint64_t TSFlags) { - switch (TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); - default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); - case X86II::Pseudo: - case X86II::RawFrm: - case X86II::AddRegFrm: - case X86II::MRMDestReg: - case X86II::MRMSrcReg: - case X86II::RawFrmImm16: - return -1; - case X86II::MRMDestMem: - return 0; - case X86II::MRMSrcMem: { - bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V; - unsigned FirstMemOp = 1; - if (HasVEX_4V) - ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). - - // FIXME: Maybe lea should have its own form? This is a horrible hack. - //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || - // Opcode == X86::LEA16r || Opcode == X86::LEA32r) - return FirstMemOp; - } - case X86II::MRM0r: case X86II::MRM1r: - case X86II::MRM2r: case X86II::MRM3r: - case X86II::MRM4r: case X86II::MRM5r: - case X86II::MRM6r: case X86II::MRM7r: - return -1; - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - return 0; - case X86II::MRM_C1: - case X86II::MRM_C2: - case X86II::MRM_C3: - case X86II::MRM_C4: - case X86II::MRM_C8: - case X86II::MRM_C9: - case X86II::MRM_E8: - case X86II::MRM_F0: - case X86II::MRM_F8: - case X86II::MRM_F9: - return -1; - } - } -} inline static bool isScale(const MachineOperand &MO) { return MO.isImm() && @@ -592,21 +127,32 @@ inline static bool isMem(const MachineInstr *MI, unsigned Op) { isLeaMem(MI, Op); } -class X86InstrInfo : public TargetInstrInfoImpl { +class X86InstrInfo : public X86GenInstrInfo { X86TargetMachine &TM; const X86RegisterInfo RI; - - /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, - /// RegOp2MemOpTable2 - Load / store folding opcode maps. + + /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, + /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps. /// - DenseMap > RegOp2MemOpTable2Addr; - DenseMap > RegOp2MemOpTable0; - DenseMap > RegOp2MemOpTable1; - DenseMap > RegOp2MemOpTable2; - + typedef DenseMap > RegOp2MemOpTableType; + RegOp2MemOpTableType RegOp2MemOpTable2Addr; + RegOp2MemOpTableType RegOp2MemOpTable0; + RegOp2MemOpTableType RegOp2MemOpTable1; + RegOp2MemOpTableType RegOp2MemOpTable2; + RegOp2MemOpTableType RegOp2MemOpTable3; + /// MemOp2RegOpTable - Load / store unfolding opcode map. /// - DenseMap > MemOp2RegOpTable; + typedef DenseMap > MemOp2RegOpTableType; + MemOp2RegOpTableType MemOp2RegOpTable; + + static void AddTableEntry(RegOp2MemOpTableType &R2MTable, + MemOp2RegOpTableType &M2RTable, + unsigned RegOp, unsigned MemOp, unsigned Flags); + + virtual void anchor(); public: explicit X86InstrInfo(X86TargetMachine &tm); @@ -634,17 +180,6 @@ public: unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const; - /// hasLoadFromStackSlot - If the specified machine instruction has - /// a load from a stack slot, return true along with the FrameIndex - /// of the loaded stack slot and the machine mem operand containing - /// the reference. If not, return false. Unlike - /// isLoadFromStackSlot, this returns true for any instructions that - /// loads from the stack. This is a hint only and may not catch all - /// cases. - bool hasLoadFromStackSlot(const MachineInstr *MI, - const MachineMemOperand *&MMO, - int &FrameIndex) const; - unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination /// stack locations as well. This uses a heuristic so it isn't @@ -652,16 +187,6 @@ public: unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const; - /// hasStoreToStackSlot - If the specified machine instruction has a - /// store to a stack slot, return true along with the FrameIndex of - /// the loaded stack slot and the machine mem operand containing the - /// reference. If not, return false. Unlike isStoreToStackSlot, - /// this returns true for any instructions that loads from the - /// stack. This is a hint only and may not catch all cases. - bool hasStoreToStackSlot(const MachineInstr *MI, - const MachineMemOperand *&MMO, - int &FrameIndex) const; - bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, @@ -669,6 +194,19 @@ public: const MachineInstr *Orig, const TargetRegisterInfo &TRI) const; + /// Given an operand within a MachineInstr, insert preceding code to put it + /// into the right format for a particular kind of LEA instruction. This may + /// involve using an appropriate super-register instead (with an implicit use + /// of the original) or creating a new virtual register and inserting COPY + /// instructions to get the data into the right class. + /// + /// Reference parameters are set to indicate how caller should add this + /// operand to the LEA instruction. + bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, + unsigned LEAOpcode, bool AllowSP, + unsigned &NewSrc, bool &isKill, + bool &isUndef, MachineOperand &ImplicitOp) const; + /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target /// may be able to convert a two-address instruction into a true @@ -699,6 +237,14 @@ public: MachineBasicBlock *FBB, const SmallVectorImpl &Cond, DebugLoc DL) const; + virtual bool canInsertSelect(const MachineBasicBlock&, + const SmallVectorImpl &Cond, + unsigned, unsigned, int&, int&, int&) const; + virtual void insertSelect(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, DebugLoc DL, + unsigned DstReg, + const SmallVectorImpl &Cond, + unsigned TrueReg, unsigned FalseReg) const; virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, @@ -728,22 +274,8 @@ public: MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl &NewMIs) const; - - virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - virtual - MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, - int FrameIx, uint64_t Offset, - const MDNode *MDPtr, - DebugLoc DL) const; + + virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; /// foldMemoryOperand - If this target supports it, fold a load or store of /// the specified stack slot into the specified machine instruction for the @@ -788,7 +320,7 @@ public: virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex = 0) const; - + /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler /// to determine if two loads are loading from the same base address. It /// should only return true if the base pointers are the same and the @@ -798,7 +330,7 @@ public: int64_t &Offset1, int64_t &Offset2) const; /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to - /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should + /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should /// be scheduled togther. On some targets if two loads are loading from /// addresses in the same cache line, it's better if they are scheduled /// together. This function takes two integers that represent the load offsets @@ -809,6 +341,9 @@ public: int64_t Offset1, int64_t Offset2, unsigned NumLoads) const; + virtual bool shouldScheduleAdjacent(MachineInstr* First, + MachineInstr *Second) const LLVM_OVERRIDE; + virtual void getNoopForMachoTarget(MCInst &NopInst) const; virtual @@ -818,32 +353,68 @@ public: /// instruction that defines the specified register class. bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; - static bool isX86_64NonExtLowByteReg(unsigned reg) { - return (reg == X86::SPL || reg == X86::BPL || - reg == X86::SIL || reg == X86::DIL); - } - static bool isX86_64ExtendedReg(const MachineOperand &MO) { if (!MO.isReg()) return false; - return isX86_64ExtendedReg(MO.getReg()); + return X86II::isX86_64ExtendedReg(MO.getReg()); } - /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or - /// higher) register? e.g. r8, xmm8, xmm13, etc. - static bool isX86_64ExtendedReg(unsigned RegNo); - /// getGlobalBaseReg - Return a virtual register initialized with the /// the global base register value. Output instructions required to /// initialize the register in the function entry block, if necessary. /// unsigned getGlobalBaseReg(MachineFunction *MF) const; - /// GetSSEDomain - Return the SSE execution domain of MI as the first element, - /// and a bitmask of possible arguments to SetSSEDomain ase the second. - std::pair GetSSEDomain(const MachineInstr *MI) const; + std::pair + getExecutionDomain(const MachineInstr *MI) const; + + void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; - /// SetSSEDomain - Set the SSEDomain of MI. - void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; + unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, + const TargetRegisterInfo *TRI) const; + unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, + const TargetRegisterInfo *TRI) const; + void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, + const TargetRegisterInfo *TRI) const; + + MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + unsigned OpNum, + const SmallVectorImpl &MOs, + unsigned Size, unsigned Alignment) const; + + bool isHighLatencyDef(int opc) const; + + bool hasHighOperandLatency(const InstrItineraryData *ItinData, + const MachineRegisterInfo *MRI, + const MachineInstr *DefMI, unsigned DefIdx, + const MachineInstr *UseMI, unsigned UseIdx) const; + + /// analyzeCompare - For a comparison instruction, return the source registers + /// in SrcReg and SrcReg2 if having two register operands, and the value it + /// compares against in CmpValue. Return true if the comparison instruction + /// can be analyzed. + virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, + unsigned &SrcReg2, + int &CmpMask, int &CmpValue) const; + + /// optimizeCompareInstr - Check if there exists an earlier instruction that + /// operates on the same source operands and sets flags in the same way as + /// Compare; remove Compare if possible. + virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, + unsigned SrcReg2, int CmpMask, int CmpValue, + const MachineRegisterInfo *MRI) const; + + /// optimizeLoadInstr - Try to remove the load by folding it to a register + /// operand at the use. We fold the load instructions if and only if the + /// def and use are in the same BB. We only look at one load and see + /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register + /// defined by the load we are trying to fold. DefMI returns the machine + /// instruction that defines FoldAsLoadDefReg, and the function returns + /// the machine instruction generated due to folding. + virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, + const MachineRegisterInfo *MRI, + unsigned &FoldAsLoadDefReg, + MachineInstr *&DefMI) const; private: MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, @@ -851,12 +422,6 @@ private: MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const; - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - unsigned OpNum, - const SmallVectorImpl &MOs, - unsigned Size, unsigned Alignment) const; - /// isFrameOperand - Return true and the FrameIndex if the specified /// operand and follow operands form a reference to the stack frame. bool isFrameOperand(const MachineInstr *MI, unsigned int Op,