X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrInfo.h;h=01b4cfffcc7c140fd99c384ff5facf65a8f1b055;hb=25ab690a43cbbb591b76d49e3595b019c32f4b3f;hp=f03f29cba5bf089e0fc51aef3d9426aa2057a0f3;hpb=4d18d5ce1e62779e7736ca0811e2e1cb06e4ea36;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index f03f29cba5b..01b4cfffcc7 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -1,4 +1,11 @@ -//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===// +//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// // // This file contains the X86 implementation of the TargetInstrInfo class. // @@ -10,6 +17,10 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" +namespace llvm { + class X86RegisterInfo; + class X86TargetMachine; + /// X86II - This namespace holds all of the target specific flags that /// instruction info tracks. /// @@ -28,7 +39,7 @@ namespace X86II { /// Raw - This form is for instructions that don't have any operands, so /// they are just a fixed opcode value, like 'leave'. RawFrm = 1, - + /// AddRegFrm - This form is used for instructions like 'push r32' that have /// their one register operand added to their opcode. AddRegFrm = 2, @@ -52,100 +63,133 @@ namespace X86II { /// to specify a source, which in this case is memory. /// MRMSrcMem = 6, - - /// MRMS[0-7][rm] - These forms are used to represent instructions that use + + /// MRM[0-7][rm] - These forms are used to represent instructions that use /// a Mod/RM byte, and use the middle field to hold extended opcode /// information. In the intel manual these are represented as /0, /1, ... /// // First, instructions that operate on a register r/m operand... - MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3 - MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7 + MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 + MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 // Next, instructions that operate on a memory r/m operand... - MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3 - MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7 + MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 + MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 - FormMask = 31, + // MRMInitReg - This form is used for instructions whose source and + // destinations are the same register. + MRMInitReg = 32, + + FormMask = 63, //===------------------------------------------------------------------===// // Actual flags... - /// Void - Set if this instruction produces no value - Void = 1 << 5, - // OpSize - Set if this instruction requires an operand size prefix (0x66), // which most often indicates that the instruction operates on 16 bit data // instead of 32 bit data. OpSize = 1 << 6, + // AsSize - Set if this instruction requires an operand size prefix (0x67), + // which most often indicates that the instruction address 16 bit address + // instead of 32 bit address (or 32 bit address in 64 bit mode). + AdSize = 1 << 7, + + //===------------------------------------------------------------------===// // Op0Mask - There are several prefix bytes that are used to form two byte - // opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to - // obtain the setting of this field. If no bits in this field is set, there - // is no prefix byte for obtaining a multibyte opcode. + // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is + // used to obtain the setting of this field. If no bits in this field is + // set, there is no prefix byte for obtaining a multibyte opcode. // - Op0Mask = 0xF << 7, - Op0Shift = 7, + Op0Shift = 8, + Op0Mask = 0xF << Op0Shift, // TB - TwoByte - Set if this instruction has a two byte opcode, which // starts with a 0x0F byte before the real opcode. - TB = 1 << 7, + TB = 1 << Op0Shift, + + // REP - The 0xF3 prefix byte indicating repetition of the following + // instruction. + REP = 2 << Op0Shift, // D8-DF - These escape opcodes are used by the floating point unit. These // values must remain sequential. - D8 = 2 << 7, D9 = 3 << 7, DA = 4 << 7, DB = 5 << 7, - DC = 6 << 7, DD = 7 << 7, DE = 8 << 7, DF = 9 << 7, + D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, + DA = 5 << Op0Shift, DB = 6 << Op0Shift, + DC = 7 << Op0Shift, DD = 8 << Op0Shift, + DE = 9 << Op0Shift, DF = 10 << Op0Shift, + + // XS, XD - These prefix codes are for single and double precision scalar + // floating point operations performed in the SSE registers. + XD = 11 << Op0Shift, XS = 12 << Op0Shift, //===------------------------------------------------------------------===// - // This three-bit field describes the size of a memory operand. Zero is + // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. + // They are used to specify GPRs and SSE registers, 64-bit operand size, + // etc. We only cares about REX.W and REX.R bits and only the former is + // statically determined. + // + REXShift = 12, + REX_W = 1 << REXShift, + + //===------------------------------------------------------------------===// + // This three-bit field describes the size of an immediate operand. Zero is // unused so that we can tell if we forgot to set a value. - Arg8 = 1 << 11, - Arg16 = 2 << 11, - Arg32 = 3 << 11, - Arg64 = 4 << 11, // 64 bit int argument for FILD64 - ArgF32 = 5 << 11, - ArgF64 = 6 << 11, - ArgF80 = 7 << 11, - ArgMask = 7 << 11, + ImmShift = 13, + ImmMask = 7 << ImmShift, + Imm8 = 1 << ImmShift, + Imm16 = 2 << ImmShift, + Imm32 = 3 << ImmShift, + Imm64 = 4 << ImmShift, //===------------------------------------------------------------------===// // FP Instruction Classification... Zero is non-fp instruction. + // FPTypeMask - Mask for all of the FP types... + FPTypeShift = 16, + FPTypeMask = 7 << FPTypeShift, + + // NotFP - The default, set for instructions that do not use FP registers. + NotFP = 0 << FPTypeShift, + // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 - ZeroArgFP = 1 << 14, + ZeroArgFP = 1 << FPTypeShift, // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst - OneArgFP = 2 << 14, + OneArgFP = 2 << FPTypeShift, // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a // result back to ST(0). For example, fcos, fsqrt, etc. // - OneArgFPRW = 3 << 14, + OneArgFPRW = 3 << FPTypeShift, // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an // explicit argument, storing the result to either ST(0) or the implicit // argument. For example: fadd, fsub, fmul, etc... - TwoArgFP = 4 << 14, + TwoArgFP = 4 << FPTypeShift, - // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. - SpecialFP = 5 << 14, + // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an + // explicit argument, but have no destination. Example: fucom, fucomi, ... + CompareFP = 5 << FPTypeShift, - // FPTypeMask - Mask for all of the FP types... - FPTypeMask = 7 << 14, + // CondMovFP - "2 operand" floating point conditional move instructions. + CondMovFP = 6 << FPTypeShift, - // PrintImplUses - Print out implicit uses in the assembly output. - PrintImplUses = 1 << 17, + // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. + SpecialFP = 7 << FPTypeShift, - OpcodeMask = 0xFF << 18, - OpcodeShift = 18, - // Bits 26 -> 31 are unused + // Bits 19 -> 23 are unused + OpcodeShift = 24, + OpcodeMask = 0xFF << OpcodeShift }; } class X86InstrInfo : public TargetInstrInfo { + X86TargetMachine &TM; const X86RegisterInfo RI; public: - X86InstrInfo(); + X86InstrInfo(X86TargetMachine &tm); /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should @@ -153,17 +197,43 @@ public: /// virtual const MRegisterInfo &getRegisterInfo() const { return RI; } - /// createNOPinstr - returns the target's implementation of NOP, which is - /// usually a pseudo-instruction, implemented by a degenerate version of - /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0' + // Return true if the instruction is a register to register move and + // leave the source and dest operands in the passed parameters. + // + bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, + unsigned& destReg) const; + unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + + /// convertToThreeAddress - This method must be implemented by targets that + /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target + /// may be able to convert a two-address instruction into a true + /// three-address instruction on demand. This allows the X86 target (for + /// example) to convert ADD and SHL instructions into LEA instructions if they + /// would require register copies due to two-addressness. + /// + /// This method returns a null pointer if the transformation cannot be + /// performed, otherwise it returns the new instruction. /// - MachineInstr* createNOPinstr() const; + virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; - /// isNOPinstr - not having a special NOP opcode, we need to know if a given - /// instruction is interpreted as an `official' NOP instr, i.e., there may be - /// more than one way to `do nothing' but only one canonical way to slack off. + /// commuteInstruction - We have a few instructions that must be hacked on to + /// commute them. /// - bool isNOPinstr(const MachineInstr &MI) const; + virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; + + + /// Insert a goto (unconditional branch) sequence to TMBB, at the + /// end of MBB + virtual void insertGoto(MachineBasicBlock& MBB, + MachineBasicBlock& TMBB) const; + + /// Reverses the branch condition of the MachineInstr pointed by + /// MI. The instruction is replaced and the new MI is returned. + virtual MachineBasicBlock::iterator + reverseBranchCondition(MachineBasicBlock::iterator MI) const; + + const TargetRegisterClass *getPointerRegClass() const; // getBaseOpcodeFor - This function returns the "base" X86 opcode for the // specified opcode number. @@ -173,4 +243,6 @@ public: } }; +} // End llvm namespace + #endif