X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrInfo.h;h=01b4cfffcc7c140fd99c384ff5facf65a8f1b055;hb=25ab690a43cbbb591b76d49e3595b019c32f4b3f;hp=d31eb9a5069461161acd3d327c989eb22da43924;hpb=3c55c54a877b3e5a79053df8f6080f505c9d1ff4;p=oota-llvm.git

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index d31eb9a5069..01b4cfffcc7 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -18,6 +18,8 @@
 #include "X86RegisterInfo.h"
 
 namespace llvm {
+  class X86RegisterInfo;
+  class X86TargetMachine;
 
 /// X86II - This namespace holds all of the target specific flags that
 /// instruction info tracks.
@@ -89,12 +91,18 @@ namespace X86II {
     // instead of 32 bit data.
     OpSize      = 1 << 6,
 
+    // AsSize - Set if this instruction requires an operand size prefix (0x67),
+    // which most often indicates that the instruction address 16 bit address
+    // instead of 32 bit address (or 32 bit address in 64 bit mode).
+    AdSize      = 1 << 7,
+
+    //===------------------------------------------------------------------===//
     // Op0Mask - There are several prefix bytes that are used to form two byte
     // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
     // used to obtain the setting of this field.  If no bits in this field is
     // set, there is no prefix byte for obtaining a multibyte opcode.
     //
-    Op0Shift    = 7,
+    Op0Shift    = 8,
     Op0Mask     = 0xF << Op0Shift,
 
     // TB - TwoByte - Set if this instruction has a two byte opcode, which
@@ -117,19 +125,29 @@ namespace X86II {
     XD = 11 << Op0Shift,   XS = 12 << Op0Shift,
 
     //===------------------------------------------------------------------===//
-    // This two-bit field describes the size of an immediate operand.  Zero is
+    // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
+    // They are used to specify GPRs and SSE registers, 64-bit operand size,
+    // etc. We only cares about REX.W and REX.R bits and only the former is
+    // statically determined.
+    //
+    REXShift    = 12,
+    REX_W       = 1 << REXShift,
+
+    //===------------------------------------------------------------------===//
+    // This three-bit field describes the size of an immediate operand.  Zero is
     // unused so that we can tell if we forgot to set a value.
-    ImmShift = 11,
+    ImmShift = 13,
     ImmMask  = 7 << ImmShift,
     Imm8     = 1 << ImmShift,
     Imm16    = 2 << ImmShift,
     Imm32    = 3 << ImmShift,
+    Imm64    = 4 << ImmShift,
 
     //===------------------------------------------------------------------===//
     // FP Instruction Classification...  Zero is non-fp instruction.
 
     // FPTypeMask - Mask for all of the FP types...
-    FPTypeShift = 13,
+    FPTypeShift = 16,
     FPTypeMask  = 7 << FPTypeShift,
 
     // NotFP - The default, set for instructions that do not use FP registers.
@@ -161,17 +179,17 @@ namespace X86II {
     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
     SpecialFP  = 7 << FPTypeShift,
 
-    // Bit 15 is unused.
-    OpcodeShift   = 17,
-    OpcodeMask    = 0xFF << OpcodeShift,
-    // Bits 25 -> 31 are unused
+    // Bits 19 -> 23 are unused
+    OpcodeShift   = 24,
+    OpcodeMask    = 0xFF << OpcodeShift
   };
 }
 
 class X86InstrInfo : public TargetInstrInfo {
+  X86TargetMachine &TM;
   const X86RegisterInfo RI;
 public:
-  X86InstrInfo();
+  X86InstrInfo(X86TargetMachine &tm);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
@@ -179,14 +197,14 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
-  //
   // Return true if the instruction is a register to register move and
   // leave the source and dest operands in the passed parameters.
   //
-  virtual bool isMoveInstr(const MachineInstr& MI,
-                           unsigned& sourceReg,
-                           unsigned& destReg) const;
-
+  bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
+                   unsigned& destReg) const;
+  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  
   /// convertToThreeAddress - This method must be implemented by targets that
   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
   /// may be able to convert a two-address instruction into a true
@@ -215,6 +233,8 @@ public:
   virtual MachineBasicBlock::iterator
   reverseBranchCondition(MachineBasicBlock::iterator MI) const;
 
+  const TargetRegisterClass *getPointerRegClass() const;
+
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
   // specified opcode number.
   //