X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrFormats.td;h=cc302663d5890c1082f9d4eca33281e91b5f0deb;hb=c848b1bbcf88ab5d8318d990612fb1fda206ea3d;hp=453a27ef490ac2ddf9315ad23412c22862a834eb;hpb=1415ca1781051bc823aa8e670dc1d0fad05bd3de;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 453a27ef490..cc302663d58 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -14,8 +14,8 @@ // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. -class Format val> { - bits<6> Value = val; +class Format val> { + bits<7> Value = val; } def Pseudo : Format<0>; def RawFrm : Format<1>; @@ -24,39 +24,32 @@ def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>; def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>; def RawFrmDstSrc: Format<10>; +def RawFrmImm8 : Format<11>; +def RawFrmImm16 : Format<12>; +def MRMXr : Format<14>; def MRMXm : Format<15>; def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; def MRM6r : Format<22>; def MRM7r : Format<23>; def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; def MRM6m : Format<30>; def MRM7m : Format<31>; -def MRM_C1 : Format<33>; -def MRM_C2 : Format<34>; -def MRM_C3 : Format<35>; -def MRM_C4 : Format<36>; -def MRM_C8 : Format<37>; -def MRM_C9 : Format<38>; -def MRM_CA : Format<39>; -def MRM_CB : Format<40>; -def MRM_E8 : Format<41>; -def MRM_F0 : Format<42>; -def RawFrmImm8 : Format<43>; -def RawFrmImm16 : Format<44>; -def MRM_F8 : Format<45>; -def MRM_F9 : Format<46>; -def MRM_D0 : Format<47>; -def MRM_D1 : Format<48>; -def MRM_D4 : Format<49>; -def MRM_D5 : Format<50>; -def MRM_D6 : Format<51>; -def MRM_D8 : Format<52>; -def MRM_D9 : Format<53>; -def MRM_DA : Format<54>; -def MRM_DB : Format<55>; -def MRM_DC : Format<56>; -def MRM_DD : Format<57>; -def MRM_DE : Format<58>; -def MRM_DF : Format<59>; +def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; +def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; +def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>; +def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>; +def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>; +def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>; +def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>; +def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>; +def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>; +def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>; +def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>; +def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>; +def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>; +def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>; +def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>; +def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>; +def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our @@ -113,17 +106,18 @@ def CD8VT4 : CD8VForm<6>; // v := 4 def CD8VT8 : CD8VForm<7>; // v := 8 // Class specifying the prefix used an opcode extension. -class Prefix val> { - bits<2> Value = val; +class Prefix val> { + bits<3> Value = val; } def NoPrfx : Prefix<0>; -def PD : Prefix<1>; -def XS : Prefix<2>; -def XD : Prefix<3>; +def PS : Prefix<1>; +def PD : Prefix<2>; +def XS : Prefix<3>; +def XD : Prefix<4>; // Class specifying the opcode map. -class Map val> { - bits<5> Value = val; +class Map val> { + bits<3> Value = val; } def OB : Map<0>; def TB : Map<1>; @@ -132,16 +126,6 @@ def TA : Map<3>; def XOP8 : Map<4>; def XOP9 : Map<5>; def XOPA : Map<6>; -def D8 : Map<7>; -def D9 : Map<8>; -def DA : Map<9>; -def DB : Map<10>; -def DC : Map<11>; -def DD : Map<12>; -def DE : Map<13>; -def DF : Map<14>; -def A6 : Map<15>; -def A7 : Map<16>; // Class specifying the encoding class Encoding val> { @@ -152,36 +136,38 @@ def EncVEX : Encoding<1>; def EncXOP : Encoding<2>; def EncEVEX : Encoding<3>; +// Operand size for encodings that change based on mode. +class OperandSize val> { + bits<2> Value = val; +} +def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. +def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. +def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. + // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. -class OpSize { bit hasOpSizePrefix = 1; } -class OpSize16 { bit hasOpSize16Prefix = 1; } +class OpSize16 { OperandSize OpSize = OpSize16; } +class OpSize32 { OperandSize OpSize = OpSize32; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class REP { bit hasREPPrefix = 1; } class TB { Map OpMap = TB; } -class D8 { Map OpMap = D8; } -class D9 { Map OpMap = D9; } -class DA { Map OpMap = DA; } -class DB { Map OpMap = DB; } -class DC { Map OpMap = DC; } -class DD { Map OpMap = DD; } -class DE { Map OpMap = DE; } -class DF { Map OpMap = DF; } class T8 { Map OpMap = T8; } class TA { Map OpMap = TA; } -class A6 { Map OpMap = A6; } -class A7 { Map OpMap = A7; } -class XOP8 { Map OpMap = XOP8; } -class XOP9 { Map OpMap = XOP9; } -class XOPA { Map OpMap = XOPA; } +class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } +class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } +class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } +class OBXS { Prefix OpPrefix = XS; } +class PS : TB { Prefix OpPrefix = PS; } class PD : TB { Prefix OpPrefix = PD; } class XD : TB { Prefix OpPrefix = XD; } class XS : TB { Prefix OpPrefix = XS; } +class T8PS : T8 { Prefix OpPrefix = PS; } class T8PD : T8 { Prefix OpPrefix = PD; } class T8XD : T8 { Prefix OpPrefix = XD; } class T8XS : T8 { Prefix OpPrefix = XS; } +class TAPS : TA { Prefix OpPrefix = PS; } class TAPD : TA { Prefix OpPrefix = PD; } class TAXD : TA { Prefix OpPrefix = XD; } class VEX { Encoding OpEnc = EncVEX; } @@ -220,7 +206,7 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bits<8> Opcode = opcod; Format Form = f; - bits<6> FormBits = Form.Value; + bits<7> FormBits = Form.Value; ImmType ImmT = i; dag OutOperandList = outs; @@ -239,18 +225,22 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, // isCodeGenonly. Needed to hide an ambiguous // AsmString from the parser, but still disassemble. - bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? - bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode? + OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change + // based on operand size of the mode + bits<2> OpSizeBits = OpSize.Value; bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? + bits<3> OpPrefixBits = OpPrefix.Value; Map OpMap = OB; // Which opcode map does this inst have? + bits<3> OpMapBits = OpMap.Value; bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? FPFormat FPForm = NotFP; // What flavor of FP instruction is this? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? Domain ExeDomain = d; bit hasREPPrefix = 0; // Does this inst have a REP prefix? Encoding OpEnc = EncNormal; // Encoding used by this instruction + bits<2> OpEncBits = OpEnc.Value; bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to @@ -270,19 +260,18 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. // TSFlags layout should be kept in sync with X86InstrInfo.h. - let TSFlags{5-0} = FormBits; - let TSFlags{6} = hasOpSizePrefix; - let TSFlags{7} = hasOpSize16Prefix; - let TSFlags{8} = hasAdSizePrefix; - let TSFlags{10-9} = OpPrefix.Value; - let TSFlags{15-11} = OpMap.Value; + let TSFlags{6-0} = FormBits; + let TSFlags{8-7} = OpSizeBits; + let TSFlags{9} = hasAdSizePrefix; + let TSFlags{12-10} = OpPrefixBits; + let TSFlags{15-13} = OpMapBits; let TSFlags{16} = hasREX_WPrefix; let TSFlags{20-17} = ImmT.Value; let TSFlags{23-21} = FPForm.Value; let TSFlags{24} = hasLockPrefix; let TSFlags{25} = hasREPPrefix; let TSFlags{27-26} = ExeDomain.Value; - let TSFlags{29-28} = OpEnc.Value; + let TSFlags{29-28} = OpEncBits; let TSFlags{37-30} = Opcode; let TSFlags{38} = hasVEX_WPrefix; let TSFlags{39} = hasVEX_4V; @@ -466,10 +455,10 @@ class PIi8 o, Format F, dag outs, dag ins, string asm, // SSE1 Instruction Templates: // // SSI - SSE1 instructions with XS prefix. -// PSI - SSE1 instructions with TB prefix. -// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. +// PSI - SSE1 instructions with PS prefix. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. // VSSI - SSE1 instructions with XS prefix in AVX form. -// VPSI - SSE1 instructions with TB prefix in AVX form, packed single. +// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. class SSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -479,11 +468,11 @@ class SSIi8 o, Format F, dag outs, dag ins, string asm, : Ii8, XS, Requires<[UseSSE1]>; class PSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, + : I, PS, Requires<[UseSSE1]>; class PSIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TB, + : Ii8, PS, Requires<[UseSSE1]>; class VSSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -491,7 +480,7 @@ class VSSI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX]>; class VPSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, + : I, PS, Requires<[HasAVX]>; // SSE2 Instruction Templates: @@ -599,11 +588,11 @@ class SS3AI o, Format F, dag outs, dag ins, string asm, Requires<[UseSSSE3]>; class MMXSS38I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, + : I, T8PS, Requires<[HasSSSE3]>; class MMXSS3AI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, + : Ii8, TAPS, Requires<[HasSSSE3]>; // SSE4.1 Instruction Templates: @@ -675,7 +664,7 @@ class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, // AVX5128I - AVX-512 instructions with T8PD prefix. // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. // AVX512PDI - AVX-512 instructions with PD, double packed. -// AVX512PSI - AVX-512 instructions with TB, single packed. +// AVX512PSI - AVX-512 instructions with PS, single packed. // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. // AVX512XSI - AVX-512 instructions with XS prefix, generic domain. // AVX512BI - AVX-512 instructions with PD, int packed domain. @@ -719,7 +708,7 @@ class AVX512PDI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX512]>; class AVX512PSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, + : I, PS, Requires<[HasAVX512]>; class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, list pattern, Domain d, InstrItinClass itin = NoItinerary> @@ -820,18 +809,6 @@ class RIi64_NOREX o, Format f, dag outs, dag ins, string asm, let CodeSize = 3; } -class RSSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : SSI, REX_W; -class RSDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : SDI, REX_W; -class RPDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : PDI, REX_W; -class VRPDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : VPDI, VEX_W; class RS2I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : S2I, REX_W; @@ -846,28 +823,28 @@ class VRS2I o, Format F, dag outs, dag ins, string asm, // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. // MMX2I - MMX / SSE2 instructions with PD prefix. -// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. -// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. class MMXI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, Requires<[HasMMX]>; + : I, PS, Requires<[HasMMX]>; class MMXI32 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, Requires<[HasMMX,Not64BitMode]>; + : I, PS, Requires<[HasMMX,Not64BitMode]>; class MMXI64 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, Requires<[HasMMX,In64BitMode]>; + : I, PS, Requires<[HasMMX,In64BitMode]>; class MMXRI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, REX_W, Requires<[HasMMX]>; + : I, PS, REX_W, Requires<[HasMMX]>; class MMX2I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : I, PD, Requires<[HasMMX]>; class MMXIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TB, Requires<[HasMMX]>; + : Ii8, PS, Requires<[HasMMX]>; class MMXID o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : Ii8, XD, Requires<[HasMMX]>;