X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrFormats.td;h=76cae1870e7762e644948025d0e3045b32ac0068;hb=39f227e4dd98d36ed852175825c3a74c05614bd6;hp=5eee625714d911229a874e7e136940464a8ced37;hpb=7f216bac5d85cd677aeac55f9dd594cdd6c82c0e;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 5eee625714d..76cae1870e7 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -41,6 +41,8 @@ def MRM_F8 : Format<41>; def MRM_F9 : Format<42>; def RawFrmImm8 : Format<43>; def RawFrmImm16 : Format<44>; +def MRM_D0 : Format<45>; +def MRM_D1 : Format<46>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our @@ -89,28 +91,37 @@ class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class SegFS { bits<2> SegOvrBits = 1; } class SegGS { bits<2> SegOvrBits = 2; } -class TB { bits<4> Prefix = 1; } -class REP { bits<4> Prefix = 2; } -class D8 { bits<4> Prefix = 3; } -class D9 { bits<4> Prefix = 4; } -class DA { bits<4> Prefix = 5; } -class DB { bits<4> Prefix = 6; } -class DC { bits<4> Prefix = 7; } -class DD { bits<4> Prefix = 8; } -class DE { bits<4> Prefix = 9; } -class DF { bits<4> Prefix = 10; } -class XD { bits<4> Prefix = 11; } -class XS { bits<4> Prefix = 12; } -class T8 { bits<4> Prefix = 13; } -class TA { bits<4> Prefix = 14; } -class TF { bits<4> Prefix = 15; } +class TB { bits<5> Prefix = 1; } +class REP { bits<5> Prefix = 2; } +class D8 { bits<5> Prefix = 3; } +class D9 { bits<5> Prefix = 4; } +class DA { bits<5> Prefix = 5; } +class DB { bits<5> Prefix = 6; } +class DC { bits<5> Prefix = 7; } +class DD { bits<5> Prefix = 8; } +class DE { bits<5> Prefix = 9; } +class DF { bits<5> Prefix = 10; } +class XD { bits<5> Prefix = 11; } +class XS { bits<5> Prefix = 12; } +class T8 { bits<5> Prefix = 13; } +class TA { bits<5> Prefix = 14; } +class A6 { bits<5> Prefix = 15; } +class A7 { bits<5> Prefix = 16; } +class T8XD { bits<5> Prefix = 17; } +class T8XS { bits<5> Prefix = 18; } +class TAXD { bits<5> Prefix = 19; } +class XOP8 { bits<5> Prefix = 20; } +class XOP9 { bits<5> Prefix = 21; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } +class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; } class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } class VEX_L { bit hasVEX_L = 1; } +class VEX_LIG { bit ignoresVEX_L = 1; } class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; } - +class MemOp4 { bit hasMemOp4Prefix = 1; } +class XOP { bit hasXOP_Prefix = 1; } class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, string AsmStr, Domain d = GenericDomain> : Instruction { @@ -134,38 +145,47 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? - bits<4> Prefix = 0; // Which prefix byte does this inst have? - bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix? + bits<5> Prefix = 0; // Which prefix byte does this inst have? + bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? FPFormat FPForm = NotFP; // What flavor of FP instruction is this? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? bits<2> SegOvrBits = 0; // Segment override prefix. Domain ExeDomain = d; - bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix? + bit hasVEXPrefix = 0; // Does this inst require a VEX prefix? bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? - bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field? - bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register + bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field? + bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to + // encode the third operand? + bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register // to be encoded in a immediate field? - bit hasVEX_L = 0; // Does this inst uses large (256-bit) registers? + bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? + bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? + bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands + bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix? // TSFlags layout should be kept in sync with X86InstrInfo.h. let TSFlags{5-0} = FormBits; let TSFlags{6} = hasOpSizePrefix; let TSFlags{7} = hasAdSizePrefix; - let TSFlags{11-8} = Prefix; - let TSFlags{12} = hasREX_WPrefix; - let TSFlags{15-13} = ImmT.Value; - let TSFlags{18-16} = FPForm.Value; - let TSFlags{19} = hasLockPrefix; - let TSFlags{21-20} = SegOvrBits; - let TSFlags{23-22} = ExeDomain.Value; - let TSFlags{31-24} = Opcode; - let TSFlags{32} = hasVEXPrefix; - let TSFlags{33} = hasVEX_WPrefix; - let TSFlags{34} = hasVEX_4VPrefix; - let TSFlags{35} = hasVEX_i8ImmReg; - let TSFlags{36} = hasVEX_L; - let TSFlags{37} = has3DNow0F0FOpcode; + let TSFlags{12-8} = Prefix; + let TSFlags{13} = hasREX_WPrefix; + let TSFlags{16-14} = ImmT.Value; + let TSFlags{19-17} = FPForm.Value; + let TSFlags{20} = hasLockPrefix; + let TSFlags{22-21} = SegOvrBits; + let TSFlags{24-23} = ExeDomain.Value; + let TSFlags{32-25} = Opcode; + let TSFlags{33} = hasVEXPrefix; + let TSFlags{34} = hasVEX_WPrefix; + let TSFlags{35} = hasVEX_4VPrefix; + let TSFlags{36} = hasVEX_4VOp3Prefix; + let TSFlags{37} = hasVEX_i8ImmReg; + let TSFlags{38} = hasVEX_L; + let TSFlags{39} = ignoresVEX_L; + let TSFlags{40} = has3DNow0F0FOpcode; + let TSFlags{41} = hasMemOp4Prefix; + let TSFlags{42} = hasXOP_Prefix; } class PseudoI pattern> @@ -317,7 +337,7 @@ class VSSI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX]>; class VPSI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, + : I, TB, Requires<[HasAVX]>; // SSE2 Instruction Templates: @@ -351,7 +371,7 @@ class VSDI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX]>; class VPDI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, + : I, TB, OpSize, Requires<[HasAVX]>; // SSE3 Instruction Templates: @@ -379,12 +399,12 @@ class S3I o, Format F, dag outs, dag ins, string asm, list pattern> // SS3AI - SSSE3 instructions with TA prefix. // // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version -// uses the MMX registers. We put those instructions here because they better -// fit into the SSSE3 instruction category rather than the MMX category. +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. class SS38I o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, T8, + : I, T8, Requires<[HasSSSE3]>; class SS3AI o, Format F, dag outs, dag ins, string asm, list pattern> @@ -413,11 +433,11 @@ class SS428I o, Format F, dag outs, dag ins, string asm, : I, T8, Requires<[HasSSE42]>; -// SS42FI - SSE 4.2 instructions with TF prefix. +// SS42FI - SSE 4.2 instructions with T8XD prefix. class SS42FI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TF, Requires<[HasSSE42]>; - + : I, T8XD, Requires<[HasSSE42orAVX]>; + // SS42AI = SSE 4.2 instructions with TA prefix class SS42AI o, Format F, dag outs, dag ins, string asm, list pattern> @@ -438,6 +458,20 @@ class AVXAIi8 o, Format F, dag outs, dag ins, string asm, : Ii8, TA, OpSize, Requires<[HasAVX]>; +// AVX2 Instruction Templates: +// Instructions introduced in AVX2 (no SSE equivalent forms) +// +// AVX28I - AVX2 instructions with T8 and OpSize prefix. +// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8. +class AVX28I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8, OpSize, + Requires<[HasAVX2]>; +class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TA, OpSize, + Requires<[HasAVX2]>; + // AES Instruction Templates: // // AES8I @@ -445,25 +479,54 @@ class AVXAIi8 o, Format F, dag outs, dag ins, string asm, class AES8I o, Format F, dag outs, dag ins, string asm, listpattern> : I, T8, - Requires<[HasAES]>; + Requires<[HasSSE2, HasAES]>; class AESAI o, Format F, dag outs, dag ins, string asm, list pattern> : Ii8, TA, - Requires<[HasAES]>; + Requires<[HasSSE2, HasAES]>; // CLMUL Instruction Templates class CLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern> + : Ii8, TA, + OpSize, Requires<[HasSSE2, HasCLMUL]>; + +class AVXCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern> : Ii8, TA, OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>; // FMA3 Instruction Templates class FMA3 o, Format F, dag outs, dag ins, string asm, listpattern> - : I, T8, + : I, T8, OpSize, VEX_4V, Requires<[HasFMA3]>; +// FMA4 Instruction Templates +class FMA4 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TA, + OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>; + +// XOP 2, 3 and 4 Operand Instruction Template +class IXOP o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + XOP, XOP9, Requires<[HasXOP]>; + +// XOP 2, 3 and 4 Operand Instruction Templates with imm byte +class IXOPi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + XOP, XOP8, Requires<[HasXOP]>; + +// XOP 5 operand instruction (VEX encoding!) +class IXOP5 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TA, + OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; + // X86-64 Instruction templates... // @@ -492,6 +555,9 @@ class RSDI o, Format F, dag outs, dag ins, string asm, class RPDI o, Format F, dag outs, dag ins, string asm, list pattern> : PDI, REX_W; +class VRPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : VPDI, VEX_W; // MMX Instruction templates // @@ -503,6 +569,11 @@ class RPDI o, Format F, dag outs, dag ins, string asm, // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. +// MMXPI - SSE 1 & 2 packed instructions for MMX with no AVX equivalents +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. No AVX equiv. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. No AVX equiv. +// MMXSS38I - SSSE3 instructions with T8 prefix for MMX registers. No AVX equiv. +// MMXSS3AI - SSSE3 instructions with TA prefix for MMX registers. No AVX equiv. class MMXI o, Format F, dag outs, dag ins, string asm, list pattern> : I, TB, Requires<[HasMMX]>; @@ -524,3 +595,21 @@ class MMXID o, Format F, dag outs, dag ins, string asm, class MMXIS o, Format F, dag outs, dag ins, string asm, list pattern> : Ii8, XS, Requires<[HasMMX]>; + +class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasXMMInt], [HasXMM]); +} +class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasXMMInt]>; +class MMXSSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasXMMInt]>; +class MMXSS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8, Requires<[HasSSSE3orAVX]>; +class MMXSS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TA, Requires<[HasSSSE3orAVX]>;