X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=84f62273d51664eaf245569c22d90d1093541689;hb=29d62bebd91fbd8a79996c3983dcd567c30c112c;hp=2258199ddf071be475f5677ccca1258613b54f56;hpb=82a87a01723c095176c6940bcc63d3a7c8007b4b;p=oota-llvm.git

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 2258199ddf0..84f62273d51 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -151,7 +151,8 @@ class Instruction {
   string Name = "";         // The opcode string for this instruction
   string Namespace = "";
 
-  dag OperandList;          // An dag containing the MI operand list.
+  dag OutOperandList;       // An dag containing the MI def operand list.
+  dag InOperandList;        // An dag containing the MI use operand list.
   string AsmString = "";    // The .s format to print the instruction with.
 
   // Pattern - Set to the DAG pattern for this instruction, if we know of one,
@@ -186,12 +187,11 @@ class Instruction {
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
+  bit isReMaterializable = 0; // Is this instruction re-materializable?
   bit isPredicable = 0;     // Is this instruction predicable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
-  bit noResults    = 0;     // Does this instruction produce no results?
-  bit clobbersPred = 0;     // Does it clobbers condition code / predicate?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
@@ -226,9 +226,13 @@ class Requires<list<Predicate> preds> {
 }
 
 /// ops definition - This is just a simple marker used to identify the operands
-/// list for an instruction.  This should be used like this:
-///     (ops R32:$dst, R32:$src) or something similar.
+/// list for an instruction. outs and ins are identical both syntatically and
+/// semantically, they are used to define def operands and use operands to
+/// improve readibility. This should be used like this:
+///     (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
 def ops;
+def outs;
+def ins;
 
 /// variable_ops definition - Mark this instruction as taking a variable number
 /// of operands.
@@ -255,14 +259,27 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+/// zero_reg definition - Special node to stand for the zero register.
+///
+def zero_reg;
 
 /// PredicateOperand - This can be used to define a predicate operand for an
 /// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
 /// AlwaysVal specifies the value of this predicate when set to "always
 /// execute".
-class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> : Operand<ty> {
+class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+  : Operand<ty> {
   let MIOperandInfo = OpTypes;
-  dag ExecuteAlways = AlwaysVal;
+  dag DefaultOps = AlwaysVal;
+}
+
+/// OptionalDefOperand - This is used to define a optional definition operand
+/// for an instruction. DefaultOps is the register the operand represents if none
+/// is supplied, e.g. zero_reg.
+class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
+  : Operand<ty> {
+  let MIOperandInfo = OpTypes;
+  dag DefaultOps = defaultops;
 }
 
 
@@ -286,21 +303,36 @@ class InstrInfo {
 
 // Standard Instructions.
 def PHI : Instruction {
-  let OperandList = (ops variable_ops);
+  let OutOperandList = (ops);
+  let InOperandList = (ops variable_ops);
   let AsmString = "PHINODE";
   let Namespace = "TargetInstrInfo";
 }
 def INLINEASM : Instruction {
-  let OperandList = (ops variable_ops);
+  let OutOperandList = (ops);
+  let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
 }
 def LABEL : Instruction {
-  let OperandList = (ops i32imm:$id);
+  let OutOperandList = (ops);
+  let InOperandList = (ops i32imm:$id);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let hasCtrlDep = 1;
 }
+def EXTRACT_SUBREG : Instruction {
+        let OutOperandList = (ops variable_ops);
+  let InOperandList = (ops variable_ops);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+}
+def INSERT_SUBREG : Instruction {
+        let OutOperandList = (ops variable_ops);
+  let InOperandList = (ops variable_ops);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+}
 
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize