X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=2258199ddf071be475f5677ccca1258613b54f56;hb=01976307d2c6328ec4dbb8e5e52770f23abd49b4;hp=eeda4f9fe06e7f5e42464781b5282ca4eeb29f88;hpb=6a648614e88586e85a36ceb5c1d3b84e4f55b458;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index eeda4f9fe06..2258199ddf0 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -12,39 +12,8 @@ // //===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// -// Value types - These values correspond to the register types defined in the -// ValueTypes.h file. If you update anything here, you must update it there as -// well! -// -class ValueType { - string Namespace = "MVT"; - int Size = size; - int Value = value; -} - -def OtherVT: ValueType<0 , 0>; // "Other" value -def i1 : ValueType<1 , 1>; // One bit boolean value -def i8 : ValueType<8 , 2>; // 8-bit integer value -def i16 : ValueType<16 , 3>; // 16-bit integer value -def i32 : ValueType<32 , 4>; // 32-bit integer value -def i64 : ValueType<64 , 5>; // 64-bit integer value -def i128 : ValueType<128, 6>; // 128-bit integer value -def f32 : ValueType<32 , 7>; // 32-bit floating point value -def f64 : ValueType<64 , 8>; // 64-bit floating point value -def f80 : ValueType<80 , 9>; // 80-bit floating point value -def f128 : ValueType<128, 10>; // 128-bit floating point value -def FlagVT : ValueType<0 , 11>; // Condition code or machine flag -def isVoid : ValueType<0 , 12>; // Produces no value -def Vector : ValueType<0 , 13>; // Abstract vector value -def v16i8 : ValueType<128, 14>; // 16 x i8 vector value -def v8i16 : ValueType<128, 15>; // 8 x i16 vector value -def v4i32 : ValueType<128, 16>; // 4 x i32 vector value -def v2i64 : ValueType<128, 17>; // 2 x i64 vector value -def v4f32 : ValueType<128, 18>; // 4 x f32 vector value -def v2f64 : ValueType<128, 19>; // 2 x f64 vector value +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" //===----------------------------------------------------------------------===// // Register file description - These classes are used to fill in the target @@ -70,19 +39,43 @@ class Register { int SpillAlignment = 0; // Aliases - A list of registers that this register overlaps with. A read or - // modification of this register can potentially read or modifie the aliased + // modification of this register can potentially read or modify the aliased // registers. - // list Aliases = []; + + // SubRegs - A list of registers that are parts of this register. Note these + // are "immediate" sub-registers and the registers within the list do not + // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], + // not [AX, AH, AL]. + list SubRegs = []; + + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = -1; } -// RegisterGroup - This can be used to define instances of Register which -// need to specify aliases. -// List "aliases" specifies which registers are aliased to this one. This -// allows the code generator to be careful not to put two values with +// RegisterWithSubRegs - This can be used to define instances of Register which +// need to specify sub-registers. +// List "subregs" specifies which registers are sub-registers to this one. This +// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. +// This allows the code generator to be careful not to put two values with // overlapping live ranges into registers which alias. -class RegisterGroup aliases> : Register { - let Aliases = aliases; +class RegisterWithSubRegs subregs> : Register { + let SubRegs = subregs; +} + +// SubRegSet - This can be used to define a specific mapping of registers to +// indices, for use as named subregs of a particular physical register. Each +// register in 'subregs' becomes an addressable subregister at index 'n' of the +// corresponding register in 'regs'. +class SubRegSet regs, list subregs> { + int index = n; + + list From = regs; + list To = subregs; } // RegisterClass - Now that all of the registers are defined, and aliases @@ -90,19 +83,25 @@ class RegisterGroup aliases> : Register { // register classes. This also defines the default allocation order of // registers by register allocators. // -class RegisterClass regTypes, int alignment, list regList> { string Namespace = namespace; - // RegType - Specify the ValueType of the registers in this register class. - // Note that all registers in a register class must have the same ValueType. + // RegType - Specify the list ValueType of the registers in this register + // class. Note that all registers in a register class must have the same + // ValueTypes. This is a list because some targets permit storing different + // types in same register, for example vector values with 128-bit total size, + // but different count/size of items, like SSE on x86. // - ValueType RegType = regType; + list RegTypes = regTypes; + + // Size - Specify the spill size in bits of the registers. A default value of + // zero lets tablgen pick an appropriate size. + int Size = 0; // Alignment - Specify the alignment required of the registers when they are // stored or loaded to memory. // - int Size = RegType.Size; int Alignment = alignment; // MemberList - Specify which registers are in this class. If the @@ -110,6 +109,10 @@ class RegisterClass MemberList = regList; + + // SubClassList - Specify which register classes correspond to subregisters + // of this class. The order should be by subregister set index. + list SubRegClassList = []; // MethodProtos/MethodBodies - These members can be used to insert arbitrary // code into a generated register class. The normal usage of this is to @@ -119,11 +122,26 @@ class RegisterClass { + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = N; +} + //===----------------------------------------------------------------------===// // Pull in the common support for scheduling // -include "../TargetSchedule.td" +include "TargetSchedule.td" +class Predicate; // Forward def //===----------------------------------------------------------------------===// // Instruction set description - These classes correspond to the C++ classes in @@ -146,6 +164,16 @@ class Instruction { list Uses = []; // Default to using no non-operand registers list Defs = []; // Default to modifying no non-operand registers + // Predicates - List of predicates which will be turned into isel matching + // code. + list Predicates = []; + + // Code size. + int CodeSize = 0; + + // Added complexity passed onto matching pattern. + int AddedComplexity = 0; + // These bits capture information about the high-level semantics of the // instruction. bit isReturn = 0; // Is this instruction a return instruction? @@ -158,12 +186,44 @@ class Instruction { bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. + bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? + bit noResults = 0; // Does this instruction produce no results? + bit clobbersPred = 0; // Does it clobbers condition code / predicate? + bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? + + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. + + string Constraints = ""; // OperandConstraint, e.g. $src = $dst. - InstrItinClass Itinerary; // Execution steps used for scheduling. + /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not + /// be encoded into the output machineinstr. + string DisableEncoding = ""; +} + +/// Imp - Helper class for specifying the implicit uses/defs set for an +/// instruction. +class Imp uses, list defs> { + list Uses = uses; + list Defs = defs; +} + +/// Predicates - These are extra conditionals which are turned into instruction +/// selector matching code. Currently each predicate is just a string. +class Predicate { + string CondString = cond; } +/// NoHonorSignDependentRounding - This predicate is true if support for +/// sign-dependent-rounding is not enabled. +def NoHonorSignDependentRounding + : Predicate<"!HonorSignDependentRoundingFPMath()">; + +class Requires preds> { + list Predicates = preds; +} /// ops definition - This is just a simple marker used to identify the operands /// list for an instruction. This should be used like this: @@ -174,13 +234,18 @@ def ops; /// of operands. def variable_ops; +/// ptr_rc definition - Mark this operand as being a pointer value whose +/// register class is resolved dynamically via a callback to TargetInstrInfo. +/// FIXME: We should probably change this to a class which contain a list of +/// flags. But currently we have but one flag. +def ptr_rc; + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. class Operand { ValueType Type = ty; string PrintMethod = "printOperand"; - int NumMIOperands = 1; dag MIOperandInfo = (ops); } @@ -190,12 +255,21 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; + +/// PredicateOperand - This can be used to define a predicate operand for an +/// instruction. OpTypes specifies the MIOperandInfo for the operand, and +/// AlwaysVal specifies the value of this predicate when set to "always +/// execute". +class PredicateOperand : Operand { + let MIOperandInfo = OpTypes; + dag ExecuteAlways = AlwaysVal; +} + + // InstrInfo - This class should only be instantiated once to provide parameters // which are global to the the target machine. // class InstrInfo { - Instruction PHIInst; - // If the target wants to associate some target-specific information with each // instruction, it should provide these two lists to indicate how to assemble // the target specific information into the 32 bits available. @@ -210,6 +284,24 @@ class InstrInfo { bit isLittleEndianEncoding = 0; } +// Standard Instructions. +def PHI : Instruction { + let OperandList = (ops variable_ops); + let AsmString = "PHINODE"; + let Namespace = "TargetInstrInfo"; +} +def INLINEASM : Instruction { + let OperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} +def LABEL : Instruction { + let OperandList = (ops i32imm:$id); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} + //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize // the format of the .s file writer. @@ -242,14 +334,6 @@ def DefaultAsmWriter : AsmWriter; // Target - This class contains the "global" target information // class Target { - // CalleeSavedRegisters - As you might guess, this is a list of the callee - // saved registers for a target. - list CalleeSavedRegisters = []; - - // PointerType - Specify the value type to be used to represent pointers in - // this target. Typically this is an i32 or i64 type. - ValueType PointerType; - // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; @@ -260,24 +344,30 @@ class Target { //===----------------------------------------------------------------------===// // SubtargetFeature - A characteristic of the chip set. // -class SubtargetFeature { +class SubtargetFeature i = []> { // Name - Feature name. Used by command line (-mattr=) to determine the // appropriate target chip. // string Name = n; - // Type - Type of attribute to be set by feature. - // - string Type = t; - // Attribute - Attribute to be set by feature. // string Attribute = a; + // Value - Value the attribute to be set to by feature. + // + string Value = v; + // Desc - Feature description. Used by command line (-mattr=) to display help // information. // string Desc = d; + + // Implies - Features that this feature implies are present. If one of those + // features isn't set, then this one shouldn't be set either. + // + list Implies = i; } //===----------------------------------------------------------------------===// @@ -300,6 +390,11 @@ class Processor f> { } //===----------------------------------------------------------------------===// -// Pull in the common support for DAG isel generation +// Pull in the common support for calling conventions. +// +include "TargetCallingConv.td" + +//===----------------------------------------------------------------------===// +// Pull in the common support for DAG isel generation. // -include "../TargetSelectionDAG.td" +include "TargetSelectionDAG.td"