X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=15213ce2831a86f30b60cd360ca2ee621f029662;hb=7b73a5d6dead3fa765cdde8316a19ac8930cc60d;hp=fce45a5c2d4e2fe803fabea8b1649a38377a8edc;hpb=7bf1c272ab27297a7bbab329de3f17ddb26e02a3;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index fce45a5c2d4..15213ce2831 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -104,11 +104,21 @@ class RegisterClass regTypes, int alignment, // int Alignment = alignment; + // CopyCost - This value is used to specify the cost of copying a value + // between two registers in this register class. The default value is one + // meaning it takes a single instruction to perform the copying. A negative + // value means copying is extremely expensive or impossible. + int CopyCost = 1; + // MemberList - Specify which registers are in this class. If the // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. // list MemberList = regList; + + // SubClassList - Specify which register classes correspond to subregisters + // of this class. The order should be by subregister set index. + list SubRegClassList = []; // MethodProtos/MethodBodies - These members can be used to insert arbitrary // code into a generated register class. The normal usage of this is to @@ -147,7 +157,8 @@ class Instruction { string Name = ""; // The opcode string for this instruction string Namespace = ""; - dag OperandList; // An dag containing the MI operand list. + dag OutOperandList; // An dag containing the MI def operand list. + dag InOperandList; // An dag containing the MI use operand list. string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, @@ -183,10 +194,11 @@ class Instruction { bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? bit isReMaterializable = 0; // Is this instruction re-materializable? + bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? - bit noResults = 0; // Does this instruction produce no results? + bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. @@ -197,27 +209,29 @@ class Instruction { string DisableEncoding = ""; } -/// Imp - Helper class for specifying the implicit uses/defs set for an -/// instruction. -class Imp uses, list defs> { - list Uses = uses; - list Defs = defs; -} - /// Predicates - These are extra conditionals which are turned into instruction /// selector matching code. Currently each predicate is just a string. class Predicate { string CondString = cond; } +/// NoHonorSignDependentRounding - This predicate is true if support for +/// sign-dependent-rounding is not enabled. +def NoHonorSignDependentRounding + : Predicate<"!HonorSignDependentRoundingFPMath()">; + class Requires preds> { list Predicates = preds; } /// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. This should be used like this: -/// (ops R32:$dst, R32:$src) or something similar. +/// list for an instruction. outs and ins are identical both syntatically and +/// semantically, they are used to define def operands and use operands to +/// improve readibility. This should be used like this: +/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; +def outs; +def ins; /// variable_ops definition - Mark this instruction as taking a variable number /// of operands. @@ -244,14 +258,27 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; +/// zero_reg definition - Special node to stand for the zero register. +/// +def zero_reg; /// PredicateOperand - This can be used to define a predicate operand for an /// instruction. OpTypes specifies the MIOperandInfo for the operand, and /// AlwaysVal specifies the value of this predicate when set to "always /// execute". -class PredicateOperand : Operand { +class PredicateOperand + : Operand { + let MIOperandInfo = OpTypes; + dag DefaultOps = AlwaysVal; +} + +/// OptionalDefOperand - This is used to define a optional definition operand +/// for an instruction. DefaultOps is the register the operand represents if none +/// is supplied, e.g. zero_reg. +class OptionalDefOperand + : Operand { let MIOperandInfo = OpTypes; - dag ExecuteAlways = AlwaysVal; + dag DefaultOps = defaultops; } @@ -275,21 +302,36 @@ class InstrInfo { // Standard Instructions. def PHI : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = "PHINODE"; let Namespace = "TargetInstrInfo"; } def INLINEASM : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; } def LABEL : Instruction { - let OperandList = (ops i32imm:$id); + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id); let AsmString = ""; let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; } +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} +def INSERT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize @@ -333,7 +375,8 @@ class Target { //===----------------------------------------------------------------------===// // SubtargetFeature - A characteristic of the chip set. // -class SubtargetFeature { +class SubtargetFeature i = []> { // Name - Feature name. Used by command line (-mattr=) to determine the // appropriate target chip. // @@ -351,6 +394,11 @@ class SubtargetFeature { // information. // string Desc = d; + + // Implies - Features that this feature implies are present. If one of those + // features isn't set, then this one shouldn't be set either. + // + list Implies = i; } //===----------------------------------------------------------------------===//