X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSystemZ%2FSystemZInstrInfo.td;h=c468b8864205ae6bb42245f0599346f05111fd34;hb=1ff62e182e648c72e6fce4f9d7911f2edfd914d2;hp=ec59e2de7015b3be3734c298dd45d22e93c868e4;hpb=76f8ae87b4705f5c08c3995948223531715a2d58;p=oota-llvm.git diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index ec59e2de701..c468b886420 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -198,8 +198,9 @@ let Defs = [CC] in { // Select instructions //===----------------------------------------------------------------------===// -def Select32 : SelectWrapper; -def Select64 : SelectWrapper; +def Select32Mux : SelectWrapper, Requires<[FeatureHighWord]>; +def Select32 : SelectWrapper; +def Select64 : SelectWrapper; defm CondStore8 : CondStores; @@ -254,6 +255,9 @@ def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), // Register moves. let neverHasSideEffects = 1 in { + // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. + def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>, + Requires<[FeatureHighWord]>; def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; } @@ -275,7 +279,10 @@ let Uses = [CC] in { // Immediate moves. let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { - // 16-bit sign-extended immediates. + // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, + // deopending on the choice of register. + def LHIMux : UnaryRIPseudo, + Requires<[FeatureHighWord]>; def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; @@ -293,7 +300,12 @@ let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, // Register loads. let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { + // Expands to L, LY or LFH, depending on the choice of register. + def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, + Requires<[FeatureHighWord]>; defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; + def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, + Requires<[FeatureHighWord]>; def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; // These instructions are split after register allocation, so we don't @@ -325,7 +337,12 @@ let Uses = [CC] in { // Register stores. let SimpleBDXStore = 1 in { + // Expands to ST, STY or STFH, depending on the choice of register. + def STMux : StoreRXYPseudo, + Requires<[FeatureHighWord]>; defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; + def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, + Requires<[FeatureHighWord]>; def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; // These instructions are split after register allocation, so we don't @@ -361,7 +378,7 @@ let mayLoad = 1, mayStore = 1 in defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; // String moves. -let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; //===----------------------------------------------------------------------===// @@ -393,11 +410,23 @@ let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in // Match 32-to-64-bit sign extensions in which the source is already // in a 64-bit register. def : Pat<(sext_inreg GR64:$src, i32), - (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; - -// 32-bit extensions from memory. -def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; + (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; + +// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, +// depending on the choice of register. +def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, + Requires<[FeatureHighWord]>; +def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; +def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, + Requires<[FeatureHighWord]>; + +// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, +// depending on the choice of register. +def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, + Requires<[FeatureHighWord]>; defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; +def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, + Requires<[FeatureHighWord]>; def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; // 64-bit extensions from memory. @@ -415,8 +444,14 @@ let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in // 32-bit extensions from registers. let neverHasSideEffects = 1 in { - def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; - def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; + // Expands to LLCR or RISB[LH]G, depending on the choice of registers. + def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>, + Requires<[FeatureHighWord]>; + def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; + // Expands to LLHR or RISB[LH]G, depending on the choice of registers. + def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>, + Requires<[FeatureHighWord]>; + def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; } // 64-bit extensions from registers. @@ -429,11 +464,23 @@ let neverHasSideEffects = 1 in { // Match 32-to-64-bit zero extensions in which the source is already // in a 64-bit register. def : Pat<(and GR64:$src, 0xffffffff), - (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; + (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; -// 32-bit extensions from memory. -def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; +// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, +// depending on the choice of register. +def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, + Requires<[FeatureHighWord]>; +def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; +def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>, + Requires<[FeatureHighWord]>; + +// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, +// depending on the choice of register. +def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, + Requires<[FeatureHighWord]>; def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; +def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>, + Requires<[FeatureHighWord]>; def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; // 64-bit extensions from memory. @@ -449,12 +496,24 @@ def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; // Truncations of 64-bit registers to 32-bit registers. def : Pat<(i32 (trunc GR64:$src)), - (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; + (EXTRACT_SUBREG GR64:$src, subreg_l32)>; -// Truncations of 32-bit registers to memory. -defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; -defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; -def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; +// Truncations of 32-bit registers to 8-bit memory. STCMux expands to +// STC, STCY or STCH, depending on the choice of register. +def STCMux : StoreRXYPseudo, + Requires<[FeatureHighWord]>; +defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; +def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, + Requires<[FeatureHighWord]>; + +// Truncations of 32-bit registers to 16-bit memory. STHMux expands to +// STH, STHY or STHH, depending on the choice of register. +def STHMux : StoreRXYPseudo, + Requires<[FeatureHighWord]>; +defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; +def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, + Requires<[FeatureHighWord]>; +def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; // Truncations of 64-bit registers to memory. defm : StoreGR64Pair; @@ -570,31 +629,39 @@ defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; // Insertions of a 16-bit immediate, leaving other bits unaffected. // We don't have or_as_insert equivalents of these operations because // OI is available instead. -let isCodeGenOnly = 1 in { - def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; - def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; -} -def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>; -def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>; -def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>; -def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>; +// +// IIxMux expands to II[LH]x, depending on the choice of register. +def IILMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; +def IIHMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; +def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; +def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; +def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; +def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; +def IILL64 : BinaryAliasRI; +def IILH64 : BinaryAliasRI; +def IIHL64 : BinaryAliasRI; +def IIHH64 : BinaryAliasRI; // ...likewise for 32-bit immediates. For GR32s this is a general // full-width move. (We use IILF rather than something like LLILF // for 32-bit moves because IILF leaves the upper 32 bits of the // GR64 unchanged.) -let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1, - isReMaterializable = 1 in { - def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; +let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { + def IIFMux : UnaryRIPseudo, + Requires<[FeatureHighWord]>; + def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; + def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; } -def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>; -def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>; +def IILF64 : BinaryAliasRIL; +def IIHF64 : BinaryAliasRIL; // An alternative model of inserthf, with the first operand being // a zero-extended value. def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), - (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit), - imm64hf32:$imm)>; + (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), + imm64hf32:$imm)>; //===----------------------------------------------------------------------===// // Addition @@ -730,21 +797,19 @@ let Defs = [CC] in { let isConvertibleToThreeAddress = 1 in { // ANDs of a 16-bit immediate, leaving other bits unaffected. // The CC result only reflects the 16-bit field, not the full register. - let isCodeGenOnly = 1 in { - def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; - def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; - } - def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>; - def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>; + def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; + def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; + def NILL64 : BinaryAliasRI; + def NILH64 : BinaryAliasRI; def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>; def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>; // ANDs of a 32-bit immediate, leaving other bits unaffected. // The CC result only reflects the 32-bit field, which means we can // use it as a zero indicator for i32 operations but not otherwise. - let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in - def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; - def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>; + let CCValues = 0xC, CompareZeroCCMask = 0x8 in + def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; + def NILF64 : BinaryAliasRIL; def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>; } @@ -777,22 +842,33 @@ let Defs = [CC] in { // ORs of a 16-bit immediate, leaving other bits unaffected. // The CC result only reflects the 16-bit field, not the full register. - let isCodeGenOnly = 1 in { - def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; - def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; - } - def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>; - def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>; - def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>; - def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>; + // + // OIxMux expands to OI[LH]x, depending on the choice of register. + def OILMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; + def OIHMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; + def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; + def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; + def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; + def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; + def OILL64 : BinaryAliasRI; + def OILH64 : BinaryAliasRI; + def OIHL64 : BinaryAliasRI; + def OIHH64 : BinaryAliasRI; // ORs of a 32-bit immediate, leaving other bits unaffected. // The CC result only reflects the 32-bit field, which means we can // use it as a zero indicator for i32 operations but not otherwise. - let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in - def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; - def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>; - def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>; + let CCValues = 0xC, CompareZeroCCMask = 0x8 in { + // Expands to OILF or OIHF, depending on the choice of register. + def OIFMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; + def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; + def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; + } + def OILF64 : BinaryAliasRIL; + def OIHF64 : BinaryAliasRIL; // ORs of memory. let CCValues = 0xC, CompareZeroCCMask = 0x8 in { @@ -824,10 +900,15 @@ let Defs = [CC] in { // XORs of a 32-bit immediate, leaving other bits unaffected. // The CC result only reflects the 32-bit field, which means we can // use it as a zero indicator for i32 operations but not otherwise. - let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in - def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; - def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>; - def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; + let CCValues = 0xC, CompareZeroCCMask = 0x8 in { + // Expands to XILF or XIHF, depending on the choice of register. + def XIFMux : BinaryRIPseudo, + Requires<[FeatureHighWord]>; + def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; + def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; + } + def XILF64 : BinaryAliasRIL; + def XIHF64 : BinaryAliasRIL; // XORs of memory. let CCValues = 0xC, CompareZeroCCMask = 0x8 in { @@ -933,12 +1014,13 @@ let Defs = [CC] in { // Forms of RISBG that only affect one word of the destination register. // They do not set CC. -let isCodeGenOnly = 1 in - def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>, - Requires<[FeatureHighWord]>; -def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>, +def RISBLL : RotateSelectAliasRIEf, Requires<[FeatureHighWord]>; +def RISBLH : RotateSelectAliasRIEf, Requires<[FeatureHighWord]>; +def RISBHL : RotateSelectAliasRIEf, Requires<[FeatureHighWord]>; +def RISBHH : RotateSelectAliasRIEf, Requires<[FeatureHighWord]>; +def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>, Requires<[FeatureHighWord]>; -def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>, +def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>, Requires<[FeatureHighWord]>; // Rotate second operand left and perform a logical operation with selected @@ -1031,23 +1113,21 @@ let mayLoad = 1, Defs = [CC] in defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; // String comparison. -let mayLoad = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, Defs = [CC], Uses = [R0L] in defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; // Test under mask. let Defs = [CC] in { - let isCodeGenOnly = 1 in { - def TMLL32 : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; - def TMLH32 : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; - } + def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; + def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; - def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR64, imm64ll16>; - def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR64, imm64lh16>; def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>; def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>; defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; } +def : CompareGR64RI; +def : CompareGR64RI; //===----------------------------------------------------------------------===// // Prefetch @@ -1080,58 +1160,58 @@ def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64; def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg; def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm; def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32; -def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32; def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64; -def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64; def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg; def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm; def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32; -def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32; def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64; -def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64; def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg; def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm; def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32; -def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32; def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64; -def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64; +def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64; def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg; def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm; def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32; -def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32; -def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32; +def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32; def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64; -def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64; -def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64; def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64; @@ -1194,11 +1274,11 @@ let Defs = [CC] in { def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; } def : Pat<(ctlz GR64:$src), - (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>; + (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. def : Pat<(i64 (anyext GR32:$src)), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; // Extend GR32s and GR64s to GR128s. let usesCustomInserter = 1 in { @@ -1208,7 +1288,7 @@ let usesCustomInserter = 1 in { } // Search a block of memory for a character. -let mayLoad = 1, Defs = [CC], Uses = [R0W] in +let mayLoad = 1, Defs = [CC], Uses = [R0L] in defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; //===----------------------------------------------------------------------===//