X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcTargetMachine.cpp;h=6979a176232a27cef2da62e55792ae33db658735;hb=515cc265c96317bb4275939a90a3d723f10e7a23;hp=2b545ac04ad06f6dca3750eabd9ba3b89a545a24;hpb=3ab48ed72fabdc41d0f36b88a08671ab8868bb1c;p=oota-llvm.git diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 2b545ac04ad..6979a176232 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -11,105 +11,117 @@ //===----------------------------------------------------------------------===// #include "SparcTargetMachine.h" +#include "SparcTargetObjectFile.h" #include "Sparc.h" -#include "llvm/Assembly/PrintModulePass.h" -#include "llvm/Module.h" -#include "llvm/PassManager.h" -#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetMachineRegistry.h" -#include "llvm/Transforms/Scalar.h" -#include +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; -namespace { +extern "C" void LLVMInitializeSparcTarget() { // Register the target. - RegisterTarget X("sparc", " SPARC"); -} - -/// SparcTargetMachine ctor - Create an ILP32 architecture model -/// -SparcTargetMachine::SparcTargetMachine(const Module &M, IntrinsicLowering *IL, - const std::string &FS) - : TargetMachine("Sparc", IL, false, 4, 4), - Subtarget(M, FS), InstrInfo(Subtarget), - FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { + RegisterTargetMachine X(TheSparcTarget); + RegisterTargetMachine Y(TheSparcV9Target); } -unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) { - std::string TT = M.getTargetTriple(); - if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-") - return 20; - - if (M.getEndianness() == Module::BigEndian && - M.getPointerSize() == Module::Pointer32) -#ifdef __sparc__ - return 20; // BE/32 ==> Prefer sparc on sparc -#else - return 5; // BE/32 ==> Prefer ppc elsewhere -#endif - else if (M.getEndianness() != Module::AnyEndianness || - M.getPointerSize() != Module::AnyPointerSize) - return 0; // Match for some other target - - return 0; -} +static std::string computeDataLayout(bool is64Bit) { + // Sparc is big endian. + std::string Ret = "E-m:e"; -/// addPassesToEmitFile - Add passes to the specified pass manager -/// to implement a static compiler for this target. -/// -bool SparcTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out, - CodeGenFileType FileType, - bool Fast) { - if (FileType != TargetMachine::AssemblyFile) return true; + // Some ABIs have 32bit pointers. + if (!is64Bit) + Ret += "-p:32:32"; - // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass()); + // Alignments for 64 bit integers. + Ret += "-i64:64"; - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); + // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. + // On SparcV9 registers can hold 64 or 32 bits, on others only 32. + if (is64Bit) + Ret += "-n32:64"; + else + Ret += "-f128:64-n32"; - // FIXME: implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); + if (is64Bit) + Ret += "-S128"; + else + Ret += "-S64"; - // FIXME: implement the switch instruction in the instruction selector. - PM.add(createLowerSwitchPass()); - - // Print LLVM code input to instruction selector: - if (PrintMachineCode) - PM.add(new PrintFunctionPass()); + return Ret; +} - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); - - PM.add(createSparcISelDag(*this)); +/// SparcTargetMachine ctor - Create an ILP32 architecture model +/// +SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool is64bit) + : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, + CM, OL), + TLOF(make_unique()), + Subtarget(TT, CPU, FS, *this, is64bit) { + initAsmInfo(); +} - // Print machine instructions as they were initially generated. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +SparcTargetMachine::~SparcTargetMachine() {} - PM.add(createRegisterAllocator()); - PM.add(createPrologEpilogCodeInserter()); +namespace { +/// Sparc Code Generator Pass Configuration Options. +class SparcPassConfig : public TargetPassConfig { +public: + SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + SparcTargetMachine &getSparcTargetMachine() const { + return getTM(); + } + + void addIRPasses() override; + bool addInstSelector() override; + void addPreEmitPass() override; +}; +} // namespace + +TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SparcPassConfig(this, PM); +} - // Print machine instructions after register allocation and prolog/epilog - // insertion. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +void SparcPassConfig::addIRPasses() { + addPass(createAtomicExpandPass(&getSparcTargetMachine())); - PM.add(createSparcFPMoverPass(*this)); + TargetPassConfig::addIRPasses(); +} - PM.add(createSparcDelaySlotFillerPass(*this)); +bool SparcPassConfig::addInstSelector() { + addPass(createSparcISelDag(getSparcTargetMachine())); + return false; +} - // Print machine instructions after filling delay slots. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +void SparcPassConfig::addPreEmitPass(){ + addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); +} - // Output assembly language. - PM.add(createSparcCodePrinterPass(Out, *this)); +void SparcV8TargetMachine::anchor() { } - // Delete the MachineInstrs we generated, since they're no longer needed. - PM.add(createMachineCodeDeleter()); - return false; +SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, + StringRef TT, StringRef CPU, + StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, + CodeModel::Model CM, + CodeGenOpt::Level OL) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { } +void SparcV9TargetMachine::anchor() { } + +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, + StringRef TT, StringRef CPU, + StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, + CodeModel::Model CM, + CodeGenOpt::Level OL) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { +}