X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcRegisterInfo.cpp;h=2acce3d15b79ffde9874ac38a1e2ab5b1a18149d;hb=c23197a26f34f559ea9797de51e187087c039c42;hp=7b8cf0e0c8967a45059f649b46776e1c3968e67f;hpb=af0492ea52fd322c4282ff637252fdba2d2159f8;p=oota-llvm.git diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 7b8cf0e0c89..2acce3d15b7 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -1,146 +1,197 @@ -//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===// -// +//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// // -// This file contains the SparcV8 implementation of the MRegisterInfo class. +// This file contains the SPARC implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// -#include "SparcV8.h" -#include "SparcV8RegisterInfo.h" +#include "Sparc.h" +#include "SparcRegisterInfo.h" +#include "SparcSubtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineLocation.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Type.h" -#include "Support/STLExtras.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/STLExtras.h" using namespace llvm; -SparcV8RegisterInfo::SparcV8RegisterInfo() - : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, - V8::ADJCALLSTACKUP) {} - -int SparcV8RegisterInfo::storeRegToStackSlot( - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const -{ - assert (RC == SparcV8::IntRegsRegisterClass - && "Can only store 32-bit values to stack slots"); - // On the order of operands here: think "[FrameIdx + 0] = SrcReg". - BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg); - return 1; +SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, + const TargetInstrInfo &tii) + : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), + Subtarget(st), TII(tii) { +} + +const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + static const unsigned CalleeSavedRegs[] = { 0 }; + return CalleeSavedRegs; } -int SparcV8RegisterInfo::loadRegFromStackSlot( - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const -{ - assert (RC == SparcV8::IntRegsRegisterClass - && "Can only load 32-bit registers from stack slots"); - BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); - return 1; +BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + Reserved.set(SP::G2); + Reserved.set(SP::G3); + Reserved.set(SP::G4); + Reserved.set(SP::O6); + Reserved.set(SP::I6); + Reserved.set(SP::I7); + Reserved.set(SP::G0); + Reserved.set(SP::G5); + Reserved.set(SP::G6); + Reserved.set(SP::G7); + return Reserved; } -int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - assert (RC == SparcV8::IntRegsRegisterClass - && "Can only copy 32-bit registers"); - BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg); - return 1; + +const TargetRegisterClass* const* +SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { + static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 }; + return CalleeSavedRegClasses; } -void SparcV8RegisterInfo:: +bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const { + return false; +} + +void SparcRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - std::cerr - << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n" - << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n"; - abort(); + MachineInstr &MI = *I; + DebugLoc dl = MI.getDebugLoc(); + int Size = MI.getOperand(0).getImm(); + if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) + Size = -Size; + if (Size) + BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); + MBB.erase(I); } -void -SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF, - MachineBasicBlock::iterator II) const { +void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + unsigned i = 0; MachineInstr &MI = *II; - while (!MI.getOperand(i).isFrameIndex()) { + DebugLoc dl = MI.getDebugLoc(); + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - int FrameIndex = MI.getOperand(i).getFrameIndex(); - - // Replace frame index with a frame pointer reference - MI.SetMachineOperandReg (i, V8::FP); + int FrameIndex = MI.getOperand(i).getIndex(); // Addressable stack objects are accessed using neg. offsets from %fp + MachineFunction &MF = *MI.getParent()->getParent(); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + - MI.getOperand(i+1).getImmedValue(); - // note: Offset < 0 - MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset); + MI.getOperand(i+1).getImm(); + + // Replace frame index with a frame pointer reference. + if (Offset >= -4096 && Offset <= 4095) { + // If the offset is small enough to fit in the immediate field, directly + // encode it. + MI.getOperand(i).ChangeToRegister(SP::I6, false); + MI.getOperand(i+1).ChangeToImmediate(Offset); + } else { + // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to + // scavenge a register here instead of reserving G1 all of the time. + unsigned OffHi = (unsigned)Offset >> 10U; + BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); + // Emit G1 = G1 + I6 + BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) + .addReg(SP::I6); + // Insert: G1+%lo(offset) into the user. + MI.getOperand(i).ChangeToRegister(SP::G1, false); + MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); + } } -void SparcV8RegisterInfo:: +void SparcRegisterInfo:: processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} -void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { +void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl = (MBBI != MBB.end() ? + MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); // Get the number of bytes to allocate from the FrameInfo int NumBytes = (int) MFI->getStackSize(); - // Emit the correct save instruction based on the number of bytes in the frame. - // Minimum stack frame size according to V8 ABI is: + // Emit the correct save instruction based on the number of bytes in + // the frame. Minimum stack frame size according to V8 ABI is: // 16 words for register window spill // 1 word for address of returned aggregate-value // + 6 words for passing parameters on the stack // ---------- // 23 words * 4 bytes per word = 92 bytes NumBytes += 92; + // Round up to next doubleword boundary -- a double-word boundary // is required by the ABI. NumBytes = (NumBytes + 7) & ~7; - BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, - V8::SP).addImm(-NumBytes).addReg(V8::SP); + NumBytes = -NumBytes; + + if (NumBytes >= -4096) { + BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) + .addReg(SP::O6).addImm(NumBytes); + } else { + // Emit this the hard way. This clobbers G1 which we always know is + // available here. + unsigned OffHi = (unsigned)NumBytes >> 10U; + BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); + // Emit G1 = G1 + I6 + BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) + .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); + BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) + .addReg(SP::O6).addReg(SP::G1); + } } -void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { +void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getOpcode() == V8::RETL && + DebugLoc dl = MBBI->getDebugLoc(); + assert(MBBI->getOpcode() == SP::RETL && "Can only put epilog before 'retl' instruction!"); - BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0); + BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) + .addReg(SP::G0); } -#include "SparcV8GenRegisterInfo.inc" - -const TargetRegisterClass* -SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { - switch (Ty->getTypeID()) { - case Type::FloatTyID: return &FPRegsInstance; - case Type::DoubleTyID: return &DFPRegsInstance; - case Type::LongTyID: - case Type::ULongTyID: return &LongRegsInstance; - default: assert(0 && "Invalid type to getClass!"); - case Type::BoolTyID: - case Type::SByteTyID: - case Type::UByteTyID: - case Type::ShortTyID: - case Type::UShortTyID: - case Type::IntTyID: - case Type::UIntTyID: - case Type::PointerTyID: return &IntRegsInstance; - } +unsigned SparcRegisterInfo::getRARegister() const { + llvm_unreachable("What is the return address register"); + return 0; +} + +unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { + llvm_unreachable("What is the frame register"); + return SP::G1; +} + +unsigned SparcRegisterInfo::getEHExceptionRegister() const { + llvm_unreachable("What is the exception register"); + return 0; } +unsigned SparcRegisterInfo::getEHHandlerRegister() const { + llvm_unreachable("What is the exception handler register"); + return 0; +} + +int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { + llvm_unreachable("What is the dwarf register number"); + return -1; +} + +#include "SparcGenRegisterInfo.inc" +