X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcISelDAGToDAG.cpp;h=7a093f08e7f0d136073bb44053ba16e0a720bfb2;hb=ea859be53ca13a1547c4675549946b74dc3c6f41;hp=b02e8600b4e602d03b10277563c26526bb81346d;hpb=dea9528f7ffd838c333fa018ab7d2fa069db91dd;p=oota-llvm.git diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index b02e8600b4e..7a093f08e7f 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -1,4 +1,4 @@ -//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// +//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// // // The LLVM Compiler Infrastructure // @@ -7,14 +7,15 @@ // //===----------------------------------------------------------------------===// // -// This file defines an instruction selector for the V8 target +// This file defines an instruction selector for the SPARC target. // //===----------------------------------------------------------------------===// -#include "SparcV8.h" -#include "SparcV8TargetMachine.h" +#include "Sparc.h" +#include "SparcTargetMachine.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" +#include "llvm/Intrinsics.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -23,57 +24,103 @@ #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Support/Debug.h" -#include +#include +#include using namespace llvm; //===----------------------------------------------------------------------===// // TargetLowering Implementation //===----------------------------------------------------------------------===// -namespace V8ISD { +namespace SPISD { enum { - FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, - CMPICC, // Compare two GPR operands, set icc. - CMPFCC, // Compare two FP operands, set fcc. - BRICC, // Branch to dest on icc condition - BRFCC, // Branch to dest on fcc condition + FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, + CMPICC, // Compare two GPR operands, set icc. + CMPFCC, // Compare two FP operands, set fcc. + BRICC, // Branch to dest on icc condition + BRFCC, // Branch to dest on fcc condition + SELECT_ICC, // Select between two values using the current ICC flags. + SELECT_FCC, // Select between two values using the current FCC flags. - Hi, Lo, // Hi/Lo operations, typically on a global address. + Hi, Lo, // Hi/Lo operations, typically on a global address. - FTOI, // FP to Int within a FP register. - ITOF, // Int to FP within a FP register. - - SELECT_ICC, // Select between two values using the current ICC flags. - SELECT_FCC, // Select between two values using the current FCC flags. - - CALL, // A V8 call instruction. - RET_FLAG, // Return with a flag operand. + FTOI, // FP to Int within a FP register. + ITOF, // Int to FP within a FP register. + + CALL, // A call instruction. + RET_FLAG // Return with a flag operand. }; } +/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC +/// condition. +static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { + switch (CC) { + default: assert(0 && "Unknown integer condition code!"); + case ISD::SETEQ: return SPCC::ICC_E; + case ISD::SETNE: return SPCC::ICC_NE; + case ISD::SETLT: return SPCC::ICC_L; + case ISD::SETGT: return SPCC::ICC_G; + case ISD::SETLE: return SPCC::ICC_LE; + case ISD::SETGE: return SPCC::ICC_GE; + case ISD::SETULT: return SPCC::ICC_CS; + case ISD::SETULE: return SPCC::ICC_LEU; + case ISD::SETUGT: return SPCC::ICC_GU; + case ISD::SETUGE: return SPCC::ICC_CC; + } +} + +/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC +/// FCC condition. +static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { + switch (CC) { + default: assert(0 && "Unknown fp condition code!"); + case ISD::SETEQ: + case ISD::SETOEQ: return SPCC::FCC_E; + case ISD::SETNE: + case ISD::SETUNE: return SPCC::FCC_NE; + case ISD::SETLT: + case ISD::SETOLT: return SPCC::FCC_L; + case ISD::SETGT: + case ISD::SETOGT: return SPCC::FCC_G; + case ISD::SETLE: + case ISD::SETOLE: return SPCC::FCC_LE; + case ISD::SETGE: + case ISD::SETOGE: return SPCC::FCC_GE; + case ISD::SETULT: return SPCC::FCC_UL; + case ISD::SETULE: return SPCC::FCC_ULE; + case ISD::SETUGT: return SPCC::FCC_UG; + case ISD::SETUGE: return SPCC::FCC_UGE; + case ISD::SETUO: return SPCC::FCC_U; + case ISD::SETO: return SPCC::FCC_O; + case ISD::SETONE: return SPCC::FCC_LG; + case ISD::SETUEQ: return SPCC::FCC_UE; + } +} + namespace { - class SparcV8TargetLowering : public TargetLowering { + class SparcTargetLowering : public TargetLowering { int VarArgsFrameOffset; // Frame offset to start of varargs area. public: - SparcV8TargetLowering(TargetMachine &TM); + SparcTargetLowering(TargetMachine &TM); virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); - /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to - /// be zero. Op is expected to be a target specific node. Used by DAG - /// combiner. - virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, - uint64_t Mask) const; + /// computeMaskedBitsForTargetNode - Determine which of the bits specified + /// in Mask are known to be either zero or one and return them in the + /// KnownZero/KnownOne bitsets. + virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + uint64_t Mask, + uint64_t &KnownZero, + uint64_t &KnownOne, + const SelectionDAG &DAG, + unsigned Depth = 0) const; virtual std::vector LowerArguments(Function &F, SelectionDAG &DAG); virtual std::pair - LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, - unsigned CC, - bool isTailCall, SDOperand Callee, ArgListTy &Args, - SelectionDAG &DAG); - virtual std::pair - LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, - SelectionDAG &DAG); + LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, + bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, + ArgListTy &Args, SelectionDAG &DAG); virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB); @@ -81,14 +128,17 @@ namespace { }; } -SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) +SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) : TargetLowering(TM) { // Set up the register classes. - addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); - addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); - addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); + addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); + addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); + addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); + // Turn FP extload into load/fextend + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + // Custom legalize GlobalAddress nodes into LO/HI parts. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool , MVT::i32, Custom); @@ -113,9 +163,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); - // Turn FP extload into load/fextend - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - // Sparc has no select or setcc: expand to SELECT_CC. setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); @@ -126,8 +173,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) // Sparc doesn't have BRCOND either, it has BR_CC. setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); + setOperationAction(ISD::BRIND, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_CC, MVT::f64, Custom); @@ -136,7 +183,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); - // V8 has no intrinsics for these particular operations. + // SPARC has no intrinsics for these particular operations. setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); setOperationAction(ISD::MEMSET, MVT::Other, Expand); setOperationAction(ISD::MEMCPY, MVT::Other, Expand); @@ -151,6 +198,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); @@ -159,73 +208,94 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) // We don't have line number support yet. setOperationAction(ISD::LOCATION, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::LABEL, MVT::Other, Expand); // RET must be custom lowered, to meet ABI requirements setOperationAction(ISD::RET , MVT::Other, Custom); - // VASTART needs to be custom lowered to use the VarArgsFrameIndex + // VASTART needs to be custom lowered to use the VarArgsFrameIndex. setOperationAction(ISD::VASTART , MVT::Other, Custom); + // VAARG needs to be lowered to not do unaligned accesses for doubles. + setOperationAction(ISD::VAARG , MVT::Other, Custom); // Use the default implementation. - setOperationAction(ISD::VAARG , MVT::Other, Expand); setOperationAction(ISD::VACOPY , MVT::Other, Expand); setOperationAction(ISD::VAEND , MVT::Other, Expand); setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - setStackPointerRegisterToSaveRestore(V8::O6); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); + setOperationAction(ISD::ConstantFP, MVT::f32, Expand); + + setStackPointerRegisterToSaveRestore(SP::O6); + if (TM.getSubtarget().isV9()) { + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + } + computeRegisterProperties(); } -const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { +const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case V8ISD::CMPICC: return "V8ISD::CMPICC"; - case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; - case V8ISD::BRICC: return "V8ISD::BRICC"; - case V8ISD::BRFCC: return "V8ISD::BRFCC"; - case V8ISD::Hi: return "V8ISD::Hi"; - case V8ISD::Lo: return "V8ISD::Lo"; - case V8ISD::FTOI: return "V8ISD::FTOI"; - case V8ISD::ITOF: return "V8ISD::ITOF"; - case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; - case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; - case V8ISD::CALL: return "V8ISD::CALL"; - case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; + case SPISD::CMPICC: return "SPISD::CMPICC"; + case SPISD::CMPFCC: return "SPISD::CMPFCC"; + case SPISD::BRICC: return "SPISD::BRICC"; + case SPISD::BRFCC: return "SPISD::BRFCC"; + case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; + case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; + case SPISD::Hi: return "SPISD::Hi"; + case SPISD::Lo: return "SPISD::Lo"; + case SPISD::FTOI: return "SPISD::FTOI"; + case SPISD::ITOF: return "SPISD::ITOF"; + case SPISD::CALL: return "SPISD::CALL"; + case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; } } /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. -bool SparcV8TargetLowering:: -isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const { +void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, + uint64_t Mask, + uint64_t &KnownZero, + uint64_t &KnownOne, + const SelectionDAG &DAG, + unsigned Depth) const { + uint64_t KnownZero2, KnownOne2; + KnownZero = KnownOne = 0; // Don't know anything. + switch (Op.getOpcode()) { - default: return false; - case V8ISD::SELECT_ICC: - case V8ISD::SELECT_FCC: - assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!"); - // These operations are masked zero if both the left and the right are zero. - return MaskedValueIsZero(Op.getOperand(0), Mask) && - MaskedValueIsZero(Op.getOperand(1), Mask); + default: break; + case SPISD::SELECT_ICC: + case SPISD::SELECT_FCC: + DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, + Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, + Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Only known if known in both the LHS and RHS. + KnownOne &= KnownOne2; + KnownZero &= KnownZero2; + break; } } - /// LowerArguments - V8 uses a very simple ABI, where all values are passed in /// either one or two GPRs, including FP values. TODO: we should pass FP values /// in FP registers for fastcc functions. std::vector -SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { +SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); SSARegMap *RegMap = MF.getSSARegMap(); std::vector ArgValues; static const unsigned ArgRegs[] = { - V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 + SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; @@ -247,12 +317,11 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { if (CurArgReg < ArgRegEnd) ++CurArgReg; ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); MF.addLiveIn(*CurArgReg++, VReg); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT != MVT::i32) { - unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext - : ISD::AssertZext; + unsigned AssertOp = ISD::AssertSext; Arg = DAG.getNode(AssertOp, MVT::i32, Arg, DAG.getValueType(ObjectVT)); Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); @@ -263,17 +332,16 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDOperand Load; if (ObjectVT == MVT::i32) { - Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } else { - unsigned LoadOp = - I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; + ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, DAG.getConstant(Offset, MVT::i32)); Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, - DAG.getSrcValue(0), ObjectVT); + NULL, 0, ObjectVT); Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); } ArgValues.push_back(Load); @@ -287,7 +355,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR // FP value is passed in an integer register. - unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); MF.addLiveIn(*CurArgReg++, VReg); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); @@ -296,7 +364,7 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); + SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); ArgValues.push_back(Load); } ArgOffset += 4; @@ -308,7 +376,8 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { if (CurArgReg < ArgRegEnd) ++CurArgReg; if (CurArgReg < ArgRegEnd) ++CurArgReg; ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); - } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && + } else if (/* FIXME: Apparently this isn't safe?? */ + 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && ((CurArgReg-ArgRegs) & 1) == 0) { // If this is a double argument and the whole thing lives on the stack, // and the argument is aligned, load the double straight from the stack. @@ -316,29 +385,28 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // because the double wouldn't be aligned! int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, - DAG.getSrcValue(0))); + ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); } else { SDOperand HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); MF.addLiveIn(*CurArgReg++, VRegHi); HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } SDOperand LoVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); MF.addLiveIn(*CurArgReg++, VRegLo); LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } // Compose the two halves together into an i64 unit. @@ -362,21 +430,21 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { VarArgsFrameOffset = ArgOffset; for (; CurArgReg != ArgRegEnd; ++CurArgReg) { - unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); MF.addLiveIn(*CurArgReg, VReg); SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), - Arg, FIPtr, DAG.getSrcValue(0))); + OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); ArgOffset += 4; } } if (!OutChains.empty()) - DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); + DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, + &OutChains[0], OutChains.size())); // Finally, inform the code generator which regs we return values in. switch (getValueType(F.getReturnType())) { @@ -386,17 +454,17 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i8: case MVT::i16: case MVT::i32: - MF.addLiveOut(V8::I0); + MF.addLiveOut(SP::I0); break; case MVT::i64: - MF.addLiveOut(V8::I0); - MF.addLiveOut(V8::I1); + MF.addLiveOut(SP::I0); + MF.addLiveOut(SP::I1); break; case MVT::f32: - MF.addLiveOut(V8::F0); + MF.addLiveOut(SP::F0); break; case MVT::f64: - MF.addLiveOut(V8::D0); + MF.addLiveOut(SP::D0); break; } @@ -404,15 +472,14 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } std::pair -SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, - bool isVarArg, unsigned CC, - bool isTailCall, SDOperand Callee, - ArgListTy &Args, SelectionDAG &DAG) { - MachineFunction &MF = DAG.getMachineFunction(); +SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, + bool RetTyIsSigned, bool isVarArg, unsigned CC, + bool isTailCall, SDOperand Callee, + ArgListTy &Args, SelectionDAG &DAG) { // Count the size of the outgoing arguments. unsigned ArgsSize = 0; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - switch (getValueType(Args[i].second)) { + switch (getValueType(Args[i].Ty)) { default: assert(0 && "Unknown value type!"); case MVT::i1: case MVT::i8: @@ -435,15 +502,14 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // Keep stack frames 8-byte aligned. ArgsSize = (ArgsSize+7) & ~7; - Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, - DAG.getConstant(ArgsSize, getPointerTy())); + Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); - SDOperand StackPtr, NullSV; + SDOperand StackPtr; std::vector Stores; std::vector RegValuesToPass; unsigned ArgOffset = 68; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - SDOperand Val = Args[i].first; + SDOperand Val = Args[i].Node; MVT::ValueType ObjectVT = Val.getValueType(); SDOperand ValToStore(0, 0); unsigned ObjSize; @@ -451,14 +517,17 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, default: assert(0 && "Unhandled argument type!"); case MVT::i1: case MVT::i8: - case MVT::i16: + case MVT::i16: { // Promote the integer to 32-bits. If the input type is signed, use a // sign extend, otherwise use a zero extend. - if (Args[i].second->isSigned()) - Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); - else - Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); + ISD::NodeType ExtendKind = ISD::ANY_EXTEND; + if (Args[i].isSExt) + ExtendKind = ISD::SIGN_EXTEND; + else if (Args[i].isZExt) + ExtendKind = ISD::ZERO_EXTEND; + Val = DAG.getNode(ExtendKind, MVT::i32, Val); // FALL THROUGH + } case MVT::i32: ObjSize = 4; @@ -499,9 +568,9 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, } // Split the value into top and bottom part. Top part goes in a reg. - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, DAG.getConstant(1, MVT::i32)); - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, DAG.getConstant(0, MVT::i32)); RegValuesToPass.push_back(Hi); @@ -517,23 +586,21 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, if (ValToStore.Val) { if (!StackPtr.Val) { - StackPtr = DAG.getRegister(V8::O6, MVT::i32); - NullSV = DAG.getSrcValue(NULL); + StackPtr = DAG.getRegister(SP::O6, MVT::i32); } SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - ValToStore, PtrOff, NullSV)); + Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); } ArgOffset += ObjSize; } // Emit all stores, make sure the occur before any copies into physregs. if (!Stores.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); static const unsigned ArgRegs[] = { - V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 + SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 }; // Build a sequence of copy-to-reg nodes chained together with token chain @@ -546,18 +613,17 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. + // Likewise ExternalSymbol -> TargetExternalSymbol. if (GlobalAddressSDNode *G = dyn_cast(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); + else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); std::vector NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - std::vector Ops; - Ops.push_back(Chain); - Ops.push_back(Callee); - if (InFlag.Val) - Ops.push_back(InFlag); - Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops); + SDOperand Ops[] = { Chain, Callee, InFlag }; + Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); InFlag = Chain.getValue(1); MVT::ValueType RetTyVT = getValueType(RetTy); @@ -567,30 +633,34 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, default: assert(0 && "Unknown value type to return!"); case MVT::i1: case MVT::i8: - case MVT::i16: - RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); + case MVT::i16: { + RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); Chain = RetVal.getValue(1); // Add a note to keep track of whether it is sign or zero extended. - RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, - MVT::i32, RetVal, DAG.getValueType(RetTyVT)); + ISD::NodeType AssertKind = ISD::AssertZext; + if (RetTyIsSigned) + AssertKind = ISD::AssertSext; + RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, + DAG.getValueType(RetTyVT)); RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); break; + } case MVT::i32: - RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); + RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); Chain = RetVal.getValue(1); break; case MVT::f32: - RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); + RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); Chain = RetVal.getValue(1); break; case MVT::f64: - RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); + RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); Chain = RetVal.getValue(1); break; case MVT::i64: - SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); - SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, + SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); + SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, Lo.getValue(2)); RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); Chain = Hi.getValue(1); @@ -604,115 +674,176 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, return std::make_pair(RetVal, Chain); } -std::pair SparcV8TargetLowering:: -LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, - SelectionDAG &DAG) { - assert(0 && "Unimp"); - abort(); +// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so +// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. +static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, + ISD::CondCode CC, unsigned &SPCC) { + if (isa(RHS) && cast(RHS)->getValue() == 0 && + CC == ISD::SETNE && + ((LHS.getOpcode() == SPISD::SELECT_ICC && + LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || + (LHS.getOpcode() == SPISD::SELECT_FCC && + LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && + isa(LHS.getOperand(0)) && + isa(LHS.getOperand(1)) && + cast(LHS.getOperand(0))->getValue() == 1 && + cast(LHS.getOperand(1))->getValue() == 0) { + SDOperand CMPCC = LHS.getOperand(3); + SPCC = cast(LHS.getOperand(2))->getValue(); + LHS = CMPCC.getOperand(0); + RHS = CMPCC.getOperand(1); + } } -SDOperand SparcV8TargetLowering:: + +SDOperand SparcTargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalAddress: { GlobalValue *GV = cast(Op)->getGlobal(); SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); - SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); - SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); + SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); + SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } case ISD::ConstantPool: { - Constant *C = cast(Op)->get(); - SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); - SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); - SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); + Constant *C = cast(Op)->getConstVal(); + SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, + cast(Op)->getAlignment()); + SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); + SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); } case ISD::FP_TO_SINT: // Convert the fp value to integer in an FP register. assert(Op.getValueType() == MVT::i32); - Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); + Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); case ISD::SINT_TO_FP: { assert(Op.getOperand(0).getValueType() == MVT::i32); SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); // Convert the int value to FP in an FP register. - return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); + return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); } case ISD::BR_CC: { SDOperand Chain = Op.getOperand(0); - SDOperand CC = Op.getOperand(1); + ISD::CondCode CC = cast(Op.getOperand(1))->get(); SDOperand LHS = Op.getOperand(2); SDOperand RHS = Op.getOperand(3); SDOperand Dest = Op.getOperand(4); + unsigned Opc, SPCC = ~0U; + + // If this is a br_cc of a "setcc", and if the setcc got lowered into + // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. + LookThroughSetCC(LHS, RHS, CC, SPCC); // Get the condition flag. + SDOperand CompareFlag; if (LHS.getValueType() == MVT::i32) { std::vector VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Flag); - std::vector Ops; - Ops.push_back(LHS); - Ops.push_back(RHS); - SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); - return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); + SDOperand Ops[2] = { LHS, RHS }; + CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); + if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); + Opc = SPISD::BRICC; } else { - SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); - return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); + CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); + if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); + Opc = SPISD::BRFCC; } + return DAG.getNode(Opc, MVT::Other, Chain, Dest, + DAG.getConstant(SPCC, MVT::i32), CompareFlag); } case ISD::SELECT_CC: { SDOperand LHS = Op.getOperand(0); SDOperand RHS = Op.getOperand(1); - unsigned CC = cast(Op.getOperand(4))->get(); + ISD::CondCode CC = cast(Op.getOperand(4))->get(); SDOperand TrueVal = Op.getOperand(2); SDOperand FalseVal = Op.getOperand(3); - + unsigned Opc, SPCC = ~0U; + // If this is a select_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. - if (isa(RHS) && cast(RHS)->getValue() == 0&& - CC == ISD::SETNE && - ((LHS.getOpcode() == V8ISD::SELECT_ICC && - LHS.getOperand(3).getOpcode() == V8ISD::CMPICC) || - (LHS.getOpcode() == V8ISD::SELECT_FCC && - LHS.getOperand(3).getOpcode() == V8ISD::CMPFCC)) && - isa(LHS.getOperand(0)) && - isa(LHS.getOperand(1)) && - cast(LHS.getOperand(0))->getValue() == 1 && - cast(LHS.getOperand(1))->getValue() == 0) { - SDOperand CMPCC = LHS.getOperand(3); - CC = cast(LHS.getOperand(2))->getValue(); - LHS = CMPCC.getOperand(0); - RHS = CMPCC.getOperand(1); - } + LookThroughSetCC(LHS, RHS, CC, SPCC); SDOperand CompareFlag; - unsigned Opc; if (LHS.getValueType() == MVT::i32) { std::vector VTs; VTs.push_back(LHS.getValueType()); // subcc returns a value VTs.push_back(MVT::Flag); - std::vector Ops; - Ops.push_back(LHS); - Ops.push_back(RHS); - CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); - Opc = V8ISD::SELECT_ICC; + SDOperand Ops[2] = { LHS, RHS }; + CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); + Opc = SPISD::SELECT_ICC; + if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); } else { - CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); - Opc = V8ISD::SELECT_FCC; + CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); + Opc = SPISD::SELECT_FCC; + if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); } return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, - DAG.getConstant(CC, MVT::i32), CompareFlag); + DAG.getConstant(SPCC, MVT::i32), CompareFlag); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, - DAG.getRegister(V8::I6, MVT::i32), - DAG.getConstant(VarArgsFrameOffset, MVT::i32)); - return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, - Op.getOperand(1), Op.getOperand(2)); + DAG.getRegister(SP::I6, MVT::i32), + DAG.getConstant(VarArgsFrameOffset, MVT::i32)); + SrcValueSDNode *SV = cast(Op.getOperand(2)); + return DAG.getStore(Op.getOperand(0), Offset, + Op.getOperand(1), SV->getValue(), SV->getOffset()); + } + case ISD::VAARG: { + SDNode *Node = Op.Val; + MVT::ValueType VT = Node->getValueType(0); + SDOperand InChain = Node->getOperand(0); + SDOperand VAListPtr = Node->getOperand(1); + SrcValueSDNode *SV = cast(Node->getOperand(2)); + SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, + SV->getValue(), SV->getOffset()); + // Increment the pointer, VAList, to the next vaarg + SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, + DAG.getConstant(MVT::getSizeInBits(VT)/8, + getPointerTy())); + // Store the incremented VAList to the legalized pointer + InChain = DAG.getStore(VAList.getValue(1), NextPtr, + VAListPtr, SV->getValue(), SV->getOffset()); + // Load the actual argument out of the pointer VAList, unless this is an + // f64 load. + if (VT != MVT::f64) { + return DAG.getLoad(VT, InChain, VAList, NULL, 0); + } else { + // Otherwise, load it as i64, then do a bitconvert. + SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); + std::vector Tys; + Tys.push_back(MVT::f64); + Tys.push_back(MVT::Other); + // Bit-Convert the value to f64. + SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), + V.getValue(1) }; + return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); + } + } + case ISD::DYNAMIC_STACKALLOC: { + SDOperand Chain = Op.getOperand(0); // Legalize the chain. + SDOperand Size = Op.getOperand(1); // Legalize the size. + + unsigned SPReg = SP::O6; + SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); + SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value + Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain + + // The resultant pointer is actually 16 words from the bottom of the stack, + // to provide a register spill area. + SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, + DAG.getConstant(96, MVT::i32)); + std::vector Tys; + Tys.push_back(MVT::i32); + Tys.push_back(MVT::Other); + SDOperand Ops[2] = { NewVal, Chain }; + return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); } case ISD::RET: { SDOperand Copy; @@ -723,77 +854,55 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { abort(); case 1: return SDOperand(); // ret void is legal - case 2: { + case 3: { unsigned ArgReg; switch(Op.getOperand(1).getValueType()) { default: assert(0 && "Unknown type to return!"); - case MVT::i32: ArgReg = V8::I0; break; - case MVT::f32: ArgReg = V8::F0; break; - case MVT::f64: ArgReg = V8::D0; break; + case MVT::i32: ArgReg = SP::I0; break; + case MVT::f32: ArgReg = SP::F0; break; + case MVT::f64: ArgReg = SP::D0; break; } Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), SDOperand()); break; } - case 3: - Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2), + case 5: + Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), SDOperand()); - Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1)); + Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); break; } - return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); } + // Frame & Return address. Currently unimplemented + case ISD::RETURNADDR: break; + case ISD::FRAMEADDR: break; } + return SDOperand(); } MachineBasicBlock * -SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, - MachineBasicBlock *BB) { +SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, + MachineBasicBlock *BB) { + const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); unsigned BROpcode; + unsigned CC; // Figure out the conditional branch opcode to use for this select_cc. switch (MI->getOpcode()) { default: assert(0 && "Unknown SELECT_CC!"); - case V8::SELECT_CC_Int_ICC: - case V8::SELECT_CC_FP_ICC: - case V8::SELECT_CC_DFP_ICC: - // Integer compare. - switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { - default: assert(0 && "Unknown integer condition code!"); - case ISD::SETEQ: BROpcode = V8::BE; break; - case ISD::SETNE: BROpcode = V8::BNE; break; - case ISD::SETLT: BROpcode = V8::BL; break; - case ISD::SETGT: BROpcode = V8::BG; break; - case ISD::SETLE: BROpcode = V8::BLE; break; - case ISD::SETGE: BROpcode = V8::BGE; break; - case ISD::SETULT: BROpcode = V8::BCS; break; - case ISD::SETULE: BROpcode = V8::BLEU; break; - case ISD::SETUGT: BROpcode = V8::BGU; break; - case ISD::SETUGE: BROpcode = V8::BCC; break; - } + case SP::SELECT_CC_Int_ICC: + case SP::SELECT_CC_FP_ICC: + case SP::SELECT_CC_DFP_ICC: + BROpcode = SP::BCOND; break; - case V8::SELECT_CC_Int_FCC: - case V8::SELECT_CC_FP_FCC: - case V8::SELECT_CC_DFP_FCC: - // FP compare. - switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { - default: assert(0 && "Unknown fp condition code!"); - case ISD::SETEQ: BROpcode = V8::FBE; break; - case ISD::SETNE: BROpcode = V8::FBNE; break; - case ISD::SETLT: BROpcode = V8::FBL; break; - case ISD::SETGT: BROpcode = V8::FBG; break; - case ISD::SETLE: BROpcode = V8::FBLE; break; - case ISD::SETGE: BROpcode = V8::FBGE; break; - case ISD::SETULT: BROpcode = V8::FBUL; break; - case ISD::SETULE: BROpcode = V8::FBULE; break; - case ISD::SETUGT: BROpcode = V8::FBUG; break; - case ISD::SETUGE: BROpcode = V8::FBUGE; break; - case ISD::SETUO: BROpcode = V8::FBU; break; - case ISD::SETO: BROpcode = V8::FBO; break; - case ISD::SETONE: BROpcode = V8::FBLG; break; - case ISD::SETUEQ: BROpcode = V8::FBUE; break; - } + case SP::SELECT_CC_Int_FCC: + case SP::SELECT_CC_FP_FCC: + case SP::SELECT_CC_DFP_FCC: + BROpcode = SP::FBCOND; break; } + + CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg @@ -811,11 +920,19 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *thisMBB = BB; MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); + BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); MachineFunction *F = BB->getParent(); F->getBasicBlockList().insert(It, copy0MBB); F->getBasicBlockList().insert(It, sinkMBB); - // Update machine-CFG edges + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), + e = BB->succ_end(); i != e; ++i) + sinkMBB->addSuccessor(*i); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while(!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); @@ -831,7 +948,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) + BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); @@ -844,56 +961,65 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, //===----------------------------------------------------------------------===// //===--------------------------------------------------------------------===// -/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine +/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine /// instructions for SelectionDAG operations. /// namespace { -class SparcV8DAGToDAGISel : public SelectionDAGISel { - SparcV8TargetLowering V8Lowering; +class SparcDAGToDAGISel : public SelectionDAGISel { + SparcTargetLowering Lowering; + + /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can + /// make the right decision when generating code for different targets. + const SparcSubtarget &Subtarget; public: - SparcV8DAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} + SparcDAGToDAGISel(TargetMachine &TM) + : SelectionDAGISel(Lowering), Lowering(TM), + Subtarget(TM.getSubtarget()) { + } - SDOperand Select(SDOperand Op); + SDNode *Select(SDOperand Op); // Complex Pattern Selectors. - bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); - bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); + bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); + bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, + SDOperand &Offset); /// InstructionSelectBasicBlock - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); virtual const char *getPassName() const { - return "SparcV8 DAG->DAG Pattern Instruction Selection"; + return "SPARC DAG->DAG Pattern Instruction Selection"; } // Include the pieces autogenerated from the target description. -#include "SparcV8GenDAGISel.inc" +#include "SparcGenDAGISel.inc" }; } // end anonymous namespace /// InstructionSelectBasicBlock - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. - DAG.setRoot(Select(DAG.getRoot())); - CodeGenMap.clear(); + DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); // Emit machine code to BB. ScheduleAndEmitDAG(DAG); } -bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, - SDOperand &Offset) { +bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, + SDOperand &Base, SDOperand &Offset) { if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32); return true; } + if (Addr.getOpcode() == ISD::TargetExternalSymbol || + Addr.getOpcode() == ISD::TargetGlobalAddress) + return false; // direct calls. if (Addr.getOpcode() == ISD::ADD) { if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) { @@ -903,166 +1029,107 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, // Constant offset from frame ref. Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); } else { - Base = Select(Addr.getOperand(0)); + Base = Addr.getOperand(0); } Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); return true; } } - if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { - Base = Select(Addr.getOperand(1)); + if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { + Base = Addr.getOperand(1); Offset = Addr.getOperand(0).getOperand(0); return true; } - if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { - Base = Select(Addr.getOperand(0)); + if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { + Base = Addr.getOperand(0); Offset = Addr.getOperand(1).getOperand(0); return true; } } - Base = Select(Addr); + Base = Addr; Offset = CurDAG->getTargetConstant(0, MVT::i32); return true; } -bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, - SDOperand &R2) { - if (Addr.getOpcode() == ISD::FrameIndex) return false; +bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, + SDOperand &R1, SDOperand &R2) { + if (Addr.getOpcode() == ISD::FrameIndex) return false; + if (Addr.getOpcode() == ISD::TargetExternalSymbol || + Addr.getOpcode() == ISD::TargetGlobalAddress) + return false; // direct calls. + if (Addr.getOpcode() == ISD::ADD) { if (isa(Addr.getOperand(1)) && Predicate_simm13(Addr.getOperand(1).Val)) return false; // Let the reg+imm pattern catch this! - if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || - Addr.getOperand(1).getOpcode() == V8ISD::Lo) + if (Addr.getOperand(0).getOpcode() == SPISD::Lo || + Addr.getOperand(1).getOpcode() == SPISD::Lo) return false; // Let the reg+imm pattern catch this! - R1 = Select(Addr.getOperand(0)); - R2 = Select(Addr.getOperand(1)); + R1 = Addr.getOperand(0); + R2 = Addr.getOperand(1); return true; } - R1 = Select(Addr); - R2 = CurDAG->getRegister(V8::G0, MVT::i32); + R1 = Addr; + R2 = CurDAG->getRegister(SP::G0, MVT::i32); return true; } -SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { +SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < V8ISD::FIRST_NUMBER) - return Op; // Already selected. - // If this has already been converted, use it. - std::map::iterator CGMI = CodeGenMap.find(Op); - if (CGMI != CodeGenMap.end()) return CGMI->second; - + N->getOpcode() < SPISD::FIRST_NUMBER) + return NULL; // Already selected. + switch (N->getOpcode()) { default: break; - case ISD::FrameIndex: { - int FI = cast(N)->getIndex(); - if (N->hasOneUse()) - return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, - CurDAG->getTargetFrameIndex(FI, MVT::i32), - CurDAG->getTargetConstant(0, MVT::i32)); - return CodeGenMap[Op] = - CurDAG->getTargetNode(V8::ADDri, MVT::i32, - CurDAG->getTargetFrameIndex(FI, MVT::i32), - CurDAG->getTargetConstant(0, MVT::i32)); - } - case ISD::ADD_PARTS: { - SDOperand LHSL = Select(N->getOperand(0)); - SDOperand LHSH = Select(N->getOperand(1)); - SDOperand RHSL = Select(N->getOperand(2)); - SDOperand RHSH = Select(N->getOperand(3)); - // FIXME, handle immediate RHS. - SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, - LHSL, RHSL); - SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, - Low.getValue(1)); - CodeGenMap[SDOperand(N, 0)] = Low; - CodeGenMap[SDOperand(N, 1)] = Hi; - return Op.ResNo ? Hi : Low; - } - case ISD::SUB_PARTS: { - SDOperand LHSL = Select(N->getOperand(0)); - SDOperand LHSH = Select(N->getOperand(1)); - SDOperand RHSL = Select(N->getOperand(2)); - SDOperand RHSH = Select(N->getOperand(3)); - // FIXME, handle immediate RHS. - SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, - LHSL, RHSL); - SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, - Low.getValue(1)); - CodeGenMap[SDOperand(N, 0)] = Low; - CodeGenMap[SDOperand(N, 1)] = Hi; - return Op.ResNo ? Hi : Low; - } case ISD::SDIV: case ISD::UDIV: { // FIXME: should use a custom expander to expose the SRA to the dag. - SDOperand DivLHS = Select(N->getOperand(0)); - SDOperand DivRHS = Select(N->getOperand(1)); + SDOperand DivLHS = N->getOperand(0); + SDOperand DivRHS = N->getOperand(1); + AddToISelQueue(DivLHS); + AddToISelQueue(DivRHS); // Set the Y register to the high-part. SDOperand TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, - CurDAG->getTargetConstant(31, MVT::i32)); + TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, + CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { - TopPart = CurDAG->getRegister(V8::G0, MVT::i32); + TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, - CurDAG->getRegister(V8::G0, MVT::i32)); + TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, + CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. - unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; - return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); + unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; + return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, + TopPart); } case ISD::MULHU: case ISD::MULHS: { // FIXME: Handle mul by immediate. - SDOperand MulLHS = Select(N->getOperand(0)); - SDOperand MulRHS = Select(N->getOperand(1)); - unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; - SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, - MulLHS, MulRHS); + SDOperand MulLHS = N->getOperand(0); + SDOperand MulRHS = N->getOperand(1); + AddToISelQueue(MulLHS); + AddToISelQueue(MulRHS); + unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; + SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, + MulLHS, MulRHS); // The high part is in the Y register. - return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); + return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); + return NULL; } - case V8ISD::CALL: - // FIXME: This is a workaround for a bug in tblgen. - { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) - // Emits: (CALL:void (tglobaladdr:i32):$dst) - // Pattern complexity = 2 cost = 1 - SDOperand N1 = N->getOperand(1); - if (N1.getOpcode() != ISD::TargetGlobalAddress && - N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; - SDOperand InFlag = SDOperand(0, 0); - SDOperand Chain = N->getOperand(0); - SDOperand Tmp0 = N1; - Chain = Select(Chain); - SDOperand Result; - if (N->getNumOperands() == 3) { - InFlag = Select(N->getOperand(2)); - Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, - Chain, InFlag); - } else { - Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, - Chain); - } - Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); - CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); - return Result.getValue(Op.ResNo); - } - P47Fail:; - } return SelectCode(Op); } -/// createSparcV8ISelDag - This pass converts a legalized DAG into a +/// createSparcISelDag - This pass converts a legalized DAG into a /// SPARC-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { - return new SparcV8DAGToDAGISel(TM); +FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { + return new SparcDAGToDAGISel(TM); }